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6/23/2013Dear registered/prospective EE457 student of Fall 2013,Many of you are graduate students entering USC and perhaps this (Fall 2013) is your first semester at USC. Welcome to USC and to the EE457 course at USC!I am your EE457 instructor. I would like you to be familiar with the EE457 syllabus and expectations of the course before the start of the semester, so that you have the advantage smoothly transitioning into USC. We teach Computer Organization with implementation emphasis. So proficiency in basic logic design is a necessary prerequisite. The first two weeks of the course are dedicated to reviewing this material. I am providing you the first two weeks' material (lecture slides, lecture videos, home work assignments, etc.) in the subsequent pages here. Please go through the same. If possible, please spend 3 weeks to go through this material and do as much of the home work as possible before coming to USC.Besides logic design basics, you are expected to have gone through a basic computer organization course where you are taught some assembly language. Make sure you know the following at minimum:PC (Program Counter), SP (Stack Pointer), IR (Instruction Register), GPR (General Purpose Registers), addressing modes, calling a subroutine and returning from a subroutine, stack, LIFO (Last-In-First-Out) aspect of Stack, Cache, Cache mapping techniques, Virtual memory, page table, TLB (Translation Look-aside buffer), ALU design (adder design and comparator design, unsigned numbers, signed arithmetic using 2's complement representation, condition code register, multi-precision arithmetic, etc.), byte addressable computer, address space, little-endian and big-endian byte orders in a word, interrupts and exceptions, etc. I review most of them but quickly.If any of the links in the next few pages does not work, try copying the whole link and then past it in a browser. Best Wishes,Gandhi Gandhi PuvvadaProfessor of Engineering Practice???????????? Ming Hsieh Department of Electrical Engineering - SystemsUniversity of Southern CaliforniaEEB200, Mail code: 2562 3740 McClintock AvenueLos Angeles, CA 90089-2562 USA?Phone: (213) 740-4461Fax: HYPERLINK "tel:%28213%29%20740-4418" \t "_blank" (213) 740-4418email: gandhi@usc.edu? EE457 Syllabus Fall of 2013: (A) go through the provided EE201L prerequisite material and do HW#1 HW#1A of EE457First week of lectures from Fall 2010 -- material leading to HW#1, HW#1A, and Lab #1?????? Main directory: engr/ee-s/457/ee457_first_ lecture/ "First week's lecture?notes and webcasts reviewing EE201L material (.jnt or .pdf files for slides + .avi or .wmv files for video):You need to install on your PC Microsoft Windows Journal Viewer to view .jnt journal?files and TechSmith TSCC Codec to view .avi video files. Some of the .jnt files were converted to .pdf format and you find links to the .pdf files next to the .jnt files.1. Microsoft Windows Journal Viewer 1.5 (not needed anymore)This helps viewing .jnt files created on Tablets. I post my slides in .jnt form. Windows journalViewer is part of Windows 7. To check to see if your computer can display a .jnt file, click on thelink below. Windows XP users, Microsoft is providing Windows journal viewer at the following link.. TechSmith TSCC Codec Version: v2.0.6 (or later version)This helps viewing .avi video files created on Camtasia. Locate TSCC codec atthe bottom of the page and click on “Free Download” .Save the tscc.exe file somewhere and execute it. This willinstall the codec. You can delete the tscc.exe file after installing the codec.Seven sets of files:1.? Chapter #1 Intro. engr/ee-s/457/ee457_first_ lecture/ee457x1_Chapter1_ microarchitecture.jnt? engr/ee-s/457/ee457_first_ lecture/1_EE457_Chapter1_ microarchitecture.avi2. DPU and CU engr/ee-s/457/ee457_first_ lecture/ee457x2_DPU_CU.jnt? engr/ee-s/457/ee457_first_ lecture/2_DPU_CU.wmv?3. Mealy machine example -- Divider Design engr/ee-s/457/ee457_first_ lecture/ee457x3_Moore_Mealy_ Divider.jnt? engr/ee-s/457/ee457_first_ lecture/3_Divider_Mealy_ example.avi?4. Data registers -- clocking and controlling engr/ee-s/457/ee457_first_ lecture/ee457x4_Data_ Registers.jnt? engr/ee-s/457/ee457_first_ lecture/4_Data_Registers_with_ Data_Enable.avi?5. Loop Counter Incrementation and Terminal Value Checking engr/ee-s/457/ee457_first_ lecture/EE457x5_P1_loop_ counter.jnt? engr/ee-s/457/ee457_first_ lecture/EE457x5_P3_loop_ counter_ee102_midterm1_Sp2005_ Q4_transparencies.jnt?? engr/ee-s/457/ee457_first_ lecture/5_Loop_Iteration_ Counter.avi?6. ME (Mutually Exclusive) and AI (All Inclusive) rules in designing a state diagram engr/ee-s/457/ee457_first_ lecture/ee457x6_P1_mutually_ exclusive.jnt? engr/ee-s/457/ee457_first_ lecture/ee457x6_P2_ME_AI_ tables.jnt?? engr/ee-s/457/ee457_first_ lecture/6_Mutually_Exclusive_ All_Inclusive.avi?7. State diagram Design examples engr/ee-s/457/ee457_first_ lecture/ee457x7_State_Diagram_ Design_examples.jnt? engr/ee-s/457/ee457_first_ lecture/7_State_Diagram_ Design_examples.avi?EE457 HW#1Homework #1 (25 page scanned pdf file) need to complete only 16 selected pages (9 pages followed by 7 pages) from the following 25-page pdf file.Work on the?9 pages: pdf pages 7 to 15 (hand-written page numbers 6 to 14).Then?work on the?7 pages: pdf pages 19 to 25 (hand-written page numbers 18 to 24).The rest of the pages are cancelled. Graduate students, who may not have had a strong undergraduate logic design course (like our EE201L) may like to work on these omitted pages for additional practice.On-campus students?are?given hard-copies of the assignment in class.????????????????State Diagram design: Practice first. Go through the pdf pages of 5/25 and 6/25. pdf page 6/25 is solution to pdf page 6/25. After going though the solution, try to recollect and draw the two state diagrams on your own?on a blank paper and then check yourself by comparing with the pdf page 6/25. You do not need to submit this page.??---------------------------------------------------Reference material on? three TTL chips used in this homework)?if you are interested in:74LS173A datasheet for reference (4-bit data register, /G1 & /G2 low-active data-enables, M & N low-active output enables, high-active clear) (PDF File) datasheet for reference (4-bit register, low-active clear) (PDF File) datasheet for reference (4-bit sync. counter, low-active sync. clear, low-active sync. load, high-active count-enables (ENP & ENT) Clear has highest priority, then load and then count-enables) (PDF File)? EE457 -- Help on HW#1 and basic logic design aspects (EE201L)??????? Provided below are some of the items from my Spring 2006 EE201L course (webcast discussions in the form of .avi files and EE201L homeworks in the form of .pdf files). Some questions from our HW#1 are from the EE201L HWs or exams.EE201L Webcasts can be found at:? Homeworks (HW#8 and HW#7) can be found at:EE201L_HW8:. Discussion on Question 3 of EE457 HW#1Please watch the first 27 minutes of the webcast on EE201L HW#8.2. If you want some exercise on state diagram design, then watch the webcast on EE201L HW#73. pdf pages 19 to 23 (hand-written page numbers?18 to 22) of the EE457 HW#1 (Q#2 of EE102L Midterm #2 of Spring 2005):Please go through the webcast titledSpring 2005 MT #2 Q#2 Small System Design (DPU, CU, waveforms)at the EE201L webcast page.4. Small System Design (lecture and slides)Right-click and download video lecture ee201_lect_Feb17_Small_Sys_Design.wmv? Additional preparation for HW#1??????? 1. Datapath Designpdf file: 04/07/2006 HW #8 Discussion: Topic: Datapath Design 04/26/2006 Small System Design Example -- GCD 2. Timing Designpdf file:? 04/14/2006 Timing Design HW #9 Discussion: Topic: Timing Analysis and Counters ??? This HW#1A?is in addition to HW#1. It consists of 4 problems.8-page homework consisting of 4 state machine designs from the EE201L class:Print last 2 pages of ? to the above 2-page item,? first 6 pages of the following to make it 8 pages. on HW#1A????? Watch these webcasts after attempting the HW#1A first by yourself. Right-click on the video file and download it.Do not stream the videos. The server is not meant for video streaming.1. The last question (Q#4) of? EE201L quiz of Spring 2010Q#4 Convert Inches to Feet and further to Yards file fileRight-click on the .avi file link below and select "Save Target as"?to download. . The first 3 questions of the EE201L RTL coding exercises: The assignment (only the first 6 pages) Q#1 Largest Number Divisible by 7 .wmv file:Right-click and?and select "Save Target as" to download ?EE201L_RTL_exercises_Spring2010_Q1.wmv Make A close to B .wmv file: Right-click and?and select "Save Target as" to download??EE201L_RTL_exercises_Spring2010_Q2.wmv #3 Copying two parts of a sorted array .wmv file: Right-click and?and select "Save Target as" to download?EE201L_RTL_exercises_Spring2010_Q3.wmv ???(B) Go through EE201L Verilog HDL lectures (you need your USC UNIX username and 10-digit student ID to access these items).EE201L Verilog lectures for the EE457 students??? 1_Verilog_Introduction_mht.jnt 1_Verilog_Introduction.avi (1 H 08 Minutes) (23 minutes) 3_behavioral_vs_structural_Verilog.jnt 3_behavioral_vs_structural_Verilog.avi (17 minutes) 4_Sequential_Statements_in_Verilog.jnt 4_Sequential_Statements_in_Verilog.avi (1 Hour) 5_blocking_non_blocking.pdf ?? (56 minutes) ? 6_RTL_coding_style.avi (33 minutes) EE201L_RTL_coding_style_verilog.pdf ee201_divider_simple.zip ? (C) Spring 2013 Quiz exam and Solution Just FYIQuiz Exam: Solution: ? ................
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