Engineer Intel SMBus Controller

[Pages:25]White Paper Sam Fleming

Technical Marketing Engineer

Intel Corporation

Interfacing I2C* Devices to an Intel? SMBus Controller

January 2009

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Executive Summary

Intel includes one or more SMBus controllers as part of their chipset devices. Its primary purpose is to permit the chipset to communicate with SMBus devices such as the SPD EEPROMs on the DIMMs, the clock driver, and various temperature sensors. Some designs incorporate I2C* slave devices on the SMBus. Being "similar" to the I2C bus, it is often difficult to program the Intel? SMBus controller to reliably communicate with these I2C slave devices. The purpose of this paper is to provide details on the various SMBus cycles that the Intel? SMBus controller can create, and then to provide guidelines on how to "analyze" the cycles supported by I2C devices to see if they can be successfully accessed by the Intel SMBus controller.

It is often difficult to program the Intel? SMBus controller to reliably communicate with I2C slave devices.

It is important to realize that sometimes it is not possible to program the SMBus controller's basic cycles to communicate with a given I2C device. The judicious use of the various blocks modes when combined with the setting of an "I2C Enable" bit (I2C_EN) (which changes the format of the some of the cycles slightly) often permits the Intel? SMBus controller to communicate successfully with I2C devices.

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Contents

Technical Challenge.................................................................................................4 Analysis of the Various Bus Cycles.............................................................................4

I2C* Cycles ..........................................................................................4 SMBus Cycles .......................................................................................6 Key Differences between SMBus and I2C* Bus Protocols .............................................13 Procedures for Interfacing I2C* Devices to an Intel? SMBus Controller..........................14 Example 1: 24LC01B-1kbit I2C* EEPROM...............................................15 Example 2: M24512-256 Kbit I2C* EEPROM ...........................................17 Example 3: LTC2483 16-Bit Analog-to-Digital Converter ..........................20 Example 4: LTC2481 16-Bit ADC ..........................................................21 Conclusion ...........................................................................................................22 References........................................................................................................... 23

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Technical Challenge

I2C * is a common interface on a wide variety of components used in IA32 designs. The Intel? SMBus controller can work with many of these devices in addition to being able to communicate with native SMBus devices.

Certain I2C protocols are different from SMBus protocols. It is often possible to get these I2C devices to work with the SMBus controller via the judicious use of specific transfer types and/or register settings in the Intel chipset.

Some of the register settings can be misleading. The Intel SMBus controller contains a setting to enable I2C mode (I2C_EN in D31:F3-0x40[2]). This is frequently confused with a specific I2C command called " I2C Read". In either case, neither of these settings put the SMBus controller into a 100% I2C mode.

This paper will discuss exactly what these two settings accomplish and show how software can leverage these two features to enable communication with several I2C devices.

Analysis of the Various Bus Cycles

This section provides details and diagrams on the various cycles that can be created by the SMBus controller. Additionally, any differences in these cycles possible with changes in configuration registers will be clearly shown.

I2C * cycles are a bit different in that the I2C specification only defines three basic cycle types: Write, Read, and Combined format cycle type. Being fairly generic, each cycle type has the ability to transfer more than one byte of data (block mode). Although this section will provide details on these three I2C cycle types, we'll see in the examples below that it's CRITICAL to analyze the EXACT cycle desired in detail. Each I2C device can configure the basic I2C "Generic" waveforms in some interesting ways.

I2C* Cycles

The I2C bus defines three basic cycle types:

? Write ? Read ? Combined Format

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These cycles are fairly generic. As can be seen in the waveforms below, each cycle type is capable of a block mode form, capable of sending multiple bytes of data per transfer.

I2C* Write Cycle Type

Figure 1. I2C* Write Cycle Type Diagram

With this transfer type, the I2C * master can send 1-N bytes of data to the I2C slave. Note that it's the slave device that determines the number of bytes to transfer by asserting the NAK at bit 37. This differs from the SMBus block mode write command in which the master determines the block write transfer size.

I2C Read Cycle Type

Figure 2. I2C Read Cycle Type Diagram

With this transfer type, the I2C master can read 1-N bytes of data from the I2C slave. Note that it's the master device that determines the number of

bytes to read by asserting the NAK at bit 37.

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I2C* Combined Format Cycle Type

Figure 3. I2C* Combined Cycle Type Diagram

The I2C* Master uses this transfer to type to do a combined W-R cycle to the slave. This cycle type can also be used to do an R-W cycle, (or even an R-R or W-W). The "Write followed by Read" sequence is by far the most common implementation of this cycle type. It's typically used to send a command to a device and then read data based on the command sent. The W-R Combined Format Cycle is also the cycle that is typically used to read from I2C EEPROMs. The initial write tells the EEPROM of the specific offset to be read from in the subsequent read cycle.

SMBus Cycles

The SMBus controller in Intel chipsets can generate several different types of SMBus cycles. Additionally, several of these cycles change when the I2C_EN bit is set. Each of these cycles will be shown in detail below.

The HCTL[4:2] bits control the exact type of cycle to be sent out on the SMBus. It is included here not only as an aid to the programmer, but also to clearly indicate that the I2C Read Command, HCTL[4:2]=110b, has nothing to do with the setting of the I2C_EN bit. This detail often confuses customers trying to determine how to create a specific cycle.

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SMBus Quick Command Cycle Type

Figure 4. SMBus Quick Command Cycle Type Diagram

A short cycle that exchanges no data with the slave.

SMBus Send Byte Cycle Type

Figure 5. SMBus Send Byte Cycle Type Diagram

An SMBus command used to write a byte of data to a slave. It differs from the Write Data Byte command in that the SMBus controller only sends the 8 bit Command Code to the slave.

The "Command Code" is an eight bit register in the SMBus controller. The contents of this register are sent during some SMBus commands. In the figures, this byte is shown as the Command Code.

It's important to realize that Command Code is nothing more than 8 bits of data sent to the slave during SMBus cycles at specific points during the cycle. It's called Command Code because this byte was designed to send a specific command to the slave device. As an example, the command code could be used during an SMBus Send Byte cycle to put a device in a specific mode dependent upon the data sent in the Command Code. Modes such as "Wake Up" and "Go to Sleep" are common.

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SMBus Receive Byte Cycle Type

Figure 6. SMBus Receive Byte Cycle Type Diagram

This SMBus command is used to read a byte of data from a slave. It differs from the Read Data Byte command in that the SMBus controller does not send the Command Code data to the slave.

SMBus Write Byte Data Cycle Type

Figure 7. SMBus Write Byte Data Cycle Type Diagram

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

S

Slave Addr

Wr A

Command Code

A

Data Byte

A P

0

Write Byte Data (HCTL[4:2]=010b) Note: I2C_EN must be 0b

This command sends the command code and one other data byte to a slave device. This command differs from the Send Byte Command in that the command code byte is sent.

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