CS 1251 – COMPUTER ARCHITECTURE



KTVR KNOWLEDGE PARK FOR ENGINEERING AND TECHNOLOGY

COIMBATORE – 641 019

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

SUBJECT : CS2253 – COMPUTER ORGANIZATION & ARCHITECTURE

CLASS : II B.E (CSE) / B.Tech (IT)

SEMESTER : IV - EVEN SEMESTER (2009- 2010)

STAFF NAME : M.ARUNA

UNIVERSITY QUESTION BANK

UNIT I - BASIC STRUCTURES OF COMPUTER

2 MARKS

UNIVERSITY QUESTIONS

1. Define Index Mode

2. What is the role of program counter in addressing?

3. Discuss the following address modes with an example : Relative , Register and indirect

4. Mention the four phases of an instruction cycle

5. Summarize the operation of a computer

6. What is stored program concept?

7. Specify the sequence of operations involved when an instruction is executed

8. State any 2 issues while encoding an instruction format

9. State any 2 addressing modes followed in RISC processors and explain them with suitable examples

10. What do you think the different factors to be considered while designing the instruction format?

11. What is load-store architecture? Discuss

12. Explain the absolute and auto –increment addressing modes with an example instruction

13. State and explain CPU performance equation.

14. Registers R1 and R2 of a computer contain the decimal values 1200 and 4600.Indicate the addressing mode and find the effective address of the memory operand in each of the following instructions:

Move 20(R1), R5

Load #3000, R5

Store R5, 30(R1) (R2)

Add – (R2), R5

15. Why data bus is bidirectional and address bus is unidirectional in most microprocessors?

16. What are the limitations of assembly language?

17. Why floating point is difficult to represent and process than integer?

18. Give an example of zero-address , one-address ,two-address and three-address instructions

19. Which data structures can be best supported using

a. Indirect addressing mode

b. Indexed addressing mode

20. Define Big Endian and Little Endian.

21. How the compiler will generate efficient and correct code?

22. The memory unit of a computer has 256 K words of 32 bits each. The computer has an instruction format with 4 fields: an operation code field, a mode field to specify one of the seven addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and the number of bits in each field if the instruction is in one memory word.

POSSIBLE QUESTIONS

1. A register is faster than main memory. Justify

2. How the slow speed I/O devices and the high speed processor are synchronized?

3. What are the techniques employed in enhancing the speed of the cache memory?

4. How can a compiler be used to improve the performance of a processor?

5. Define Byte Addressable Memory.

6. How to access the successive bytes and the successive words in the BAM?

7. How a zero address is actually implemented? Give an eg.

8. How would you represent a variable in the assembly language?

9. Define Safe push / Safe pop.

10. What is an assembler directive? Give egs.

11. Steps to improve the Clock Rate.

12. What is the role of a Program Counter?

13. Syntax for ALP statement.

14. Define Effective Address.

15. What is IR?

16. Define MAR and MDR

17. Define ISR

18. How interrupts are handled?

19. Single bus / Multiple bus architecture

20. Elapsed time and Processor time

21. What is a bus?

22. Types of buses

23. Define clock rate

24. What is multitasking?

25. Define Superscalar operation

26. Define word length

27. Define Address space.

28. What is the address space of a processor whose address is 16 bits?

29. What do you mean by BAM?

30. Types of instructions based on their functionality.

31. Types of instructions based on their structure.

32. Distinguish memory mapped I/O and programmed I/O.

16 MARKS

UNIVERSITY QUESTIONS

1. Describe the different classes of Instruction format with example and different addressing modes?

2. Explain stored program organization and stack organization

3. With the help of a block diagram, explain the basic functional units of a computer.

4. What is a stack? Illustrate the use of stack in subroutine processing with suitable diagram. Discuss different addressing modes in detail.

5. Briefly explain 6 I/O operations with an example .Illustrate memory read and write operations

6. What are the various types of ISAs (Instruction Set Architecture) possible? Discuss.

Discuss the various issues to be considered while designing the ISA of a processor.

7. What is a Stack? State some uses of the same. Show how a Stack can be implemented using auto increment and auto decrement addressing modes. Write an assembly language program using the assembly language you are familiar with to add a sequence of n numbers. Give appropriate comments.

8. Explain in detail the different types of instructions that are supported in a typical processor. Registers R1 and R2 of a computer contain the decimal values 1200 and 2400 respectively. What is the effective address of the memory operand in each of the following instructions?

a. Load 20(R1) , R5

b. Add –(R2) , R5

c. Move #3000 , R5

d. Sub (R1)+ , R5

POSSIBLE QUESTIONS

1. Functional units of a computer

2. Ways to improve the performance of a computer

3. Memory addressing and operations

4. Addressing modes

5. Basic operational concepts

6. Basic Input /Output operations

7. Stacks And Queues

UNIT I – ALU DESIGN

2 MARKS

UNIVERSITY QUESTIONS

1. Define overflow

2. Write IEEE standard for floating point format. Mention the scale factor

3. Discuss the principle of operation of a carry look ahead adder.

4. Write IEEE standard for a double precision floating point format and explain the various fields.

5. Discuss the booth’s multiplication algorithm

6. What are the advantages of the booth’s multiplication technique?

7. Discuss the principle of operation of a carry save adder

8. How many addition/subtraction done for the multiplier value 01110110 if we use booth algorithm?

9. What are the difficulties faced when we use floating point arithmetic?

10. Why floating point number is more difficult to represent and process than an integer?

11. Draw a full adder circuit and give the truth table.

12. What is the purpose of guard bits in floating point operations?

13. Give the booth’s recoding and bit-pair recoding of the number 1000111101000101

POSSIBLE QUESTIONS

1. What is a n bit ripple carry adder?

2. Give the logic expression for sum and carry in a full adder circuit

3. What is the delay for sum and carry in n bit ripple carry adder?

4. What is the delay for sum and carry in n bit carry look ahead adder?

5. How would you extend a carry look-ahead header for longer operands?

6. What are the components of an array multiplication cell?

7. Give the booth multiplier recoding table.

8. What do you mean by skipping over 1’s?

9. Give examples for worst case, ordinary and good multipliers under the booth multiplication scheme?

10. What is the multiplication technique that reduces the number of summands by n/2 for n bit operands?

11. How many levels of CSA are required for k summands?

12. What are the steps in restoring division?

13. What are the steps in non-restoring division?

14. What is binary normalization of a floating point number? Give an example

15. How to represent the special values using floating point representation?

16. Name some operations that may lead to exceptions

17. What are guard bits? Mention their significance

18. What are the different ways of truncation?

19. What is a sticky bit?

20. What is the mantissa part of a floating point number?

21. How would you calculate the exponent part of a floating point number?

16 MARKS

UNIVERSITY QUESTIONS

1. Describe a multiplication speedup technique

2. Explain the floating point addition – subtraction unit

3. Give the organization of a floating point adder/subtractor unit handling IEEE standard floating point representations and explain the sequence of operations done her.

4. Discuss the Booth’s multiplication algorithm. Simulate the same for 25 * (-16)

5. Derive and draw in flowcharts for adding and subtracting two floating point binary numbers

6. Draw and explain the flowchart for binary division

7. Draw the block diagram of a sequential circuit binary multiplier and explain its operation. Demonstrate the operation of the above multiplier with the help of a multiplication example. Consider two 4 bit numbers

8. Explain with the help of a block diagram , the operation of a basic n bit arithmetic logic unit

9. Give the schematic of a 4 x 4 array multiplier and explain .What is the worst case delay in this case? Give the organization of a sequential binary multiplier and explain

10. State the non-restoring division technique. Simulate the same for 20/8.waht is carry – save adder? Discuss with an example

11. Discuss the booth’s multiplication algorithm .Give the booth’s multiplier for 1100110101111.Discuss any one binary division algorithm. Simulate the same for 33/8

12. Discuss the restoring division algorithm and give a possible implementation for it .simulate the same for 24/9

13. Show how floating point addition / subtraction are carried out on a standard representation. Discuss the modified booth’s algorithm. What are its advantages?

14. Discuss the principle of operation of carry look-ahead adders. Design a 64 bit adder that uses 4 16 bit carry look-ahead adders along with additional logic to generate c16, c32, c48 and c64 from c0 and the gi ii and pi ii variables. Also calculate the delay for generating s 63 and c64

15. Discuss the operation of a floating point adder/subtractor unit. Simulate the addition operation ion the operands a = 010001011011, b = 101111101010. With a five bit signed excess – 15 exponent and six bit normalized fractional mantissa

16. Discuss the principle of operation of carry – look ahead adders. Discuss the restoring division algorithm

17. Multiply the following pair of signed 2’s complement numbers using the booth’s algorithm. Multiplicand = 010111 and multiplier = 110110. Consider a 16 bit, floating point number with a 6 bit exponent and a 9 bit fractional mantissa where

the base is 2 and the exponent is represented in excess-31 format. Add the numbers a, b formatted as follows

A = 0100001 111111110

B = 0011111 001010101. Give the answer in the normalized form. Use rounding to get the 9 bit mantissa

18. Design a 4 bit carry look-ahead adder using gate level. Using this block design, a 64 bit carry look-ahead adder. Compare its speed with 64 bit ripple carry adder

19. What are the algorithms available in division? Explain any one algorithm with suitable example

20. Give the block diagram of the hardware implementation of addition and subtraction of signed number and explain the operations with flowchart. Explain the representations of floating point numbers in detail

21. Design a multiplier that multiplies two 4 – bit numbers. Describe the algorithm for integer division with suitable example

22. Explain in detail the principle of carry look-ahead adder. Show how 16 bit CLA S can be constructed from 4 bit adders. Perform the division on the following 5 bit unsigned integer using no – restoring division ;10101/00101

23. Explain the working of floating point adder/subtractor. Multiply the following pair of signed 2’s complement numbers using bit pair recoding of the multipliers ; a= 010111 , b= 101100

24. Discuss the principle of operation of a carry look-ahead adder. Discuss the non – restoring division algorithm. Simulate the same for 23/5.

25. Discuss the concept of bit pair recoding. Multiply the following pair of signed 2’s c numbers using bit pair recoded multiplier: Multiplicand = 110011 and Multiplier = 101100. Simulate the addition and subtraction operations ( A + (OR) – B) on the operands , A = 0 10001 011011 , B = 1 01111 101010 with a 5 bit signed excess- 15 exponent and a 6 bit normalized fractional mantissa

UNIT II - BASIC PROCESSING UNIT

2 MARKS

UNIVERSITY QUESTIONS

1. What is meant by hard wired control?

2. Differentiate hardwired and micro programmed control.

3. Draw the 20 bits micro instruction code format.

4. Specify the sequence of operations involved when an instruction is executed.

5. Discuss briefly the basic organization of a micro programmed control unit.

6. What are the relative advantages and disadvantages of micro programmed control over hardwired control?

7. Point out the advantages and disadvantages of hardwired control over micro programmed control.

8. What are the advantages and disadvantages of hardwired and micro programmed control?

9. What are the relative merits of horizontal and vertical microinstruction formats?

10. What are the differences between hardwired and micro programmed control unit?

11. State the differences between hardwired and micro programmed control unit.

12. Why is the wait – for – memory- function-completed step needed when reading form or writing to the main memory?

13. Discuss the principle of operation of a micro programmed control unit.

POSSIBLE QUESTIONS

1. What are the different phases of instruction execution?

2. Mention the functions of MAR, MDR, IR, PC.

3. What are the control signals associated with each register?

4. Define datapath

5. What is processor clock?

6. What is multiphase clocking?

7. What is the purpose of WMFC signal?

8. What is the purpose of multiplexer in giving input to ALU?

9. What is a register file?

10. What is an incrementer?

11. Define control word, microroutine, microinstructions , control store , microprogram counter, micro operation , horizontal organization and vertical organization

12. What is microprogram sequencing? What is bit ORing technique?

13. What is prefetching microinstructions?

14. Define emulation

16 MARKS

UNIVERSITY QUESTIONS

1. Explain the micro programmed control unit organization.

2. Describe any one of the hardwired control method to generate the control signals.

3. Give a typical single bus organization connecting the various parts of the CPU and show how an instruction like SUB RO, R1, (R2) gets executed here . Assume that the instruction is a one word instruction and R0, R1 are source operands where (R2) is the destination operand.

4. With neat diagrams, explain the design of a control unit.

5. Define micro program. Explain with a suitable example.

6. Explain the organization of a hardwired – control unit. Illustrate your answer with a neat block diagram.

7. Consider the following instruction:

a. ADD (R0)+ , R1, R2

where the first two are source operands and the third is the destination operand . Show the control sequence to execute this instruction for a single bus organization assuming the instruction itself is only a one word instruction.

b. What are the features to be considered while designing the instruction formats of a processor? Discuss in detail.

8. Give the organization of a typical hard wired control unit and explain the functions performed by various blocks. Discuss the data flow for a sample instruction.

9. Discuss the various hazards that might arise in a pipeline. What are the remedies commonly adopted to overcome/minimize these hazards?

10. Write the sequence of control steps required for the singe bus organization for executing the following instruction:

a. MUL (R0)+ , R1,R2 , where the first two are the source operands and the third is the destination operand . Assume the instruction itself is only a one – word instruction. What are the drawbacks of the single bus organization? Show how the multi bus organization overcomes them.

11. What is meant by microprogrammed control unit? Give the organization of a typical microprogrammed control unit and explain the functions performed by the various blocks. Critically compare it with a hardwired control unit.

12. Give the organization of a typical hard wired control unit and explain the functions performed by the various blocks. Discuss the dataflow for a sample instruction.

POSSIBLE QUESTIONS

1. Explain single bus organization

2. Explain how an instruction is being executed?

3. Write a note on multiple bus organization

4. Explain hardwired control

5. Explain in detail microprogrammed control

UNIT III – PIPELINING

2 MARKS

UNIVERSITY QUESTIONS

1. State the different types of hazards that can occur in a pipeline.

2. What is the ideal speedup of a pipeline with m stages? State the assumptions made.

3. What is the ideal speedup that can be expected in a pipeline with k stages?

4. Consider a unpipelined machine that has 10 ns clock cycles and uses four cycles for ALU operations and branches and five cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose that due to clock skew and setup, pipelining the machine adds 1 ns of overhead to the clock. Ignoring any latency impact, how much speedup in the instruction execution rate will we gain form a pipeline?

5. Define pipeline speedup.

6. How do control instructions like branch, cause problems in a pipelined processor?

7. What is the ideal speedup expected in a pipelined architecture with ‘n’n stages? Justify your answer.

8. What are the difficulties caused by instruction pipeline do deviate from normal operation?

9. Define pipeline speedup.

POSSIBLE QUESTIONS

1. What is pipelining?

2. What is assembly line operation?

3. What are the different stages in 4 stage pipeline?

4. What is the role of buffer in a pipeline?

5. What does the field next address of an instruction stand for

6. What is a stall in a pipeline?

7. What is a hazard? What are the different types of hazards?

8. What is a bubble?

9. Give examples for data hazard.

10. What do you mean by operand forwarding?

11. What is side effect?

12. Define branch penalty.

13. What is the purpose of dispatch unit?

14. What do you mean by branch folding?

15. Define dynamic count of programs.

16. Define branch delay slot.

17. What do you mean by delayed branching?

18. What is speculative execution?

19. Differentiate static and dynamic branch prediction techniques

20. What are the different states of dynamic branch prediction?

21. How to maintain state information in dynamic branch prediction?

22. Define super scalar operation

23. What do you mean by handling multiple issues?

24. What are precise and imprecise exceptions?

25. What do you mean by commitment of an instruction?

26. What is a commitment unit?

27. Define register renaming

28. What is a reorder buffer?

29. What do you mean by retiring of an instruction?

30. What is a deadlock?

16 MARKS

UNIVERSITY QUESTIONS

1. What is ideal speedup of a pipelined machine with κ pipeline stages? What are the factors that prevent us from achieving this ideal speed up? Discuss.

2. Show the structure of an m-stage pipeline. With a neat sketch, explain a 2 – staged pipelined microprogram control unit.

3. Assuming a 4-segment pipeline, discuss the operation of this with a space –time diagram. What are its advantages and disadvantages over a non-pipelined design? What is an arithmetic pipeline? Discuss with a typical example.

4. Discuss the concept of pipelining .What is ideal speedup in a pipelined organization? Discuss the various factors that might reduce the speedup and suggest ways of overcoming or minimizing them.

5. Explain the execution of an instruction with a diagram. Explain the function of a 6 segment pipeline and draw a space diagram for a six segment pipeline showing the time it takes to process 8 tasks.

6. Explain how the performance of the instruction pipeline can be improved. Explain multiple bus organization in detail.

7. Explain how pipelining helps to speed up the processor. Discuss the hazards that have to be taken care of in a pipelined processor .Give the sequence of control signals to be generated to fetch an instruction from memory in a single bus organization.

8. Discuss the various hazards that might arise in a pipeline. What are the remedies commonly adopted to overcome /minimize these hazards?

POSSIBLE QUESTIONS

1. Describe data hazards in detail.

2. Explain instruction hazards. What is the impact of branch instruction?

3. Explain the influence of instruction sets

4. What are the different data path and control considerations

5. Describe in detail super scalar operation

UNIT IV - MEMORY SYSTEM

2 MARKS

UNIVERSITY QUESTIONS

1. Define virtual memory.

2. What is the necessary for memory hierarchy?

3. What is meant by interleaved memory organization?

4. A two way set associative cache memory uses blocks of four words. The cache can accommodate a total of 2048 words from main memory. The main memory size is 128K X 32. What is the size of the cache memory?

5. An address space is specified by 24 bits and the corresponding memory space by 16 bits. If a page consists of 2K words. How many pages and blocks are there in the system?

6. Draw the memory hierarchy diagram and mention about the size, cost and speed of operation of each block.

7. Discuss about the different types of ROMs.

8. Define Average memory access time for a computer system with 2 levels of caches.

9. How do you construct a 8 M X 32 memory using 512 K x 8 memory chips?

10. What is meant by memory interleaving? Show the distribution of addresses for a memory system consisting of two banks of four 1K memory modules to form an 8K memory system. Give the main memory address format.

11. What is a write buffer? How is it useful?

12. What is a TLB? What is its significance?

13. What is meant by memory interleaving?

14. Define the average memory access time for a system with a main memory and two levels of cache and explain.

15. What is an associative memory?

16. Distinguish between the write – through and write – back policies pointing out their relative merits and demerits.

17. What is an interleaved memory system? Discuss.

18. What is a TLB? How is it useful?

19. Write down the expression for the average memory access time for a system with three levels of caches with hit ratios h1,h2 and h3 and access times tc1, tc2,tc3 and main memory access time tm. Explain the same.

20. Distinguish between memory mapped I/O and I/O mapped I/O.

21. Define the term locality of reference.

22. How many 128 X 8 RAM chips are needed to provide a memory capacity of 2048 bytes and also find how many lines of the address bus must be used to access 2048 bytes of memory?

23. Why does DMA have priority over the CPU when both request a memory transfer?

24. An eight-way set-associative cache consists of a total of 256 blocks. The main memory contains 8192 blocks, each consisting of 128 words.

(a) How many bits are there in the main memory address?

(b) How many bits are there in the TAG, SET and WORD fields?

16 MARKS

UNIVERSITY QUESTIONS

1. With neat diagram explain the internal organization of bit cells in a memory chip.

2. What is memory interleaving? Explain the Addressing of Multiple-Module Memory system.

3. What is meant by virtual memory? Discuss the implementation of any one virtual memory management system. A system has 48-bit virtual addresses: 36 bit physical addresses and 128 MB of main memory. If the system uses 4096-byts pages, how many virtual and physical pages can the address spaces support? How many page frames of main memory are there?

4. Discuss the different read/write policies used in cache memories bringing the relative advantages and disadvantages of each of them. What is an associative memory? How is it different form the conventional memory? An eight-way set-associative cache is used in a computer in which the real memory size is 232 bytes . The line size is 16 bytes and there are 2 10 lines per set. Calculate the cache size and tag length.

5. What is meant by virtual memory ?Explain how virtual address is mapped to physical address using paging technique

6. Explain the various mapping processes of cache memory.

7. How is memory classified? Explain. Explain with the help of a diagram , the organization of bit cells in a memory chip. The circuit has to be organized as a 128 X 8 memory

8. Discuss the relative advantages and disadvantages of the three mapping techniques used in cache memories. Consider a main memory of size 128 MB and a cache of size 64 KB. If the block size is 64 bytes and the cache uses 4 – way set –associative mapping, give the main memory address format and explain.

9. Discuss any one virtual memory management technique in detail. What are associative memories? How are they constructed? How are they useful?

10. Draw the basic cell of an associative memory unit. Show how an m X n memory is constructed using this basic cell. Discuss the relative advantages and disadvantages of the three mapping techniques used in cache memories.

11. Discuss the different types of Cache mapping techniques. A 2 – way set associative cache memory uses blocks of 4 words. The cache can accommodate a total of 2048 words from main memory. The main memory size is 128 K X 32. What is the size of the cache memory? Show how the cache is organized?

12. The access time of a cache memory is 100 ns and that of main memory is 1000 ns. It is estimated that 80% of the memory requests are for read and the remaining 20% for write. The hit ratio for read accesses only is 0.9. A write through procedure is used.

a. What is the average access time of the system considering only memory read cycles?

b. What is the average access time of the system for both read and write requests?

c. What is the hit ratio taking into consideration the write cycles?

13. Discuss the concept of virtual memory and explain any one virtual memory management technique. A virtual memory system has an address space of 8 K word, a memory space of 4 K words , and page and block sizes of 1 K words . The following page reference changes occur during a given time interval. Only page changes are listed, if same page is referenced again, it is not listed twice.

4 2 0 1 2 6 1 4 0 1 0 2 3 5 7

Determine the four pages that are resident in main memory after each page reference if the replacement algorithm used is LRU.

14. Explain the concept of virtual memory with any one virtual memory management techniques. Give the basic cell of an associative memory and explain its operation.

15. A computer system has a main memory consisting of 1M 16 bit words. It also has a 4K word cache organized in the block set associative manner, with 4 blocks per

set and 64 words per block. Calculate the number of bits in each of the TAG, SET and WORD fields of the main memory address format. Assume that the cache is initially empty. Suppose that the processor fetches 4352 words from location 0, 1, 2 … 4351, in that order. It then repeats this fetch sequence more times. If the cache is 10 times faster than the main memory, estimate the improvement factor resulting from the use of the cache. Assume that the LRU algorithm is used for block replacement.

16. Explain the concept of virtual memory. Discuss the same for a paged memory management technique.

17. Discuss the various mapping techniques used in cache memories. A computer system has a main memory consisting of 16 M words. It also has a 32 K word cache organized in the block- set – associative manner, with 4 blocks per set and 128 words per block. Calculate the number of bits in each of the TAG, SET and WORD fields of the main memory address format. How will the main memory address look like for a fully associative mapped cache?

18. Explain the concept of virtual memory with any 1 virtual memory management technique. Give the basic cell of an associative memory and explain its operations .Show how associative memories can be constructed using this basic cell.

19. Explain in detail about associative mapping and set associative mapping in cache memory organization. Write a short note on replacement policies.

20. What is virtual memory? Explain how the logical address is translated into physical addresses in the virtual memory system with a neat diagram. Describe the organization of a typical RAM chip.

21. Explain the organization of magnetic disk in detail. A digital computer has a memory unit of 64 K X 16 and cache memory of 1 K words. The cache uses direct mapping with a block size of 4 words. How many bits are there in the TAG, INDEX, BLOCK and WORD fields of the address format? How many blocks can the cache accommodate?

22. Discuss the address translation mechanism and the different page replacement policies used in a virtual memory system. A byte addressable computer has a small data cache capable of holding 8 32 bit words. Each cache block contains 1 32 bit word. When a given program is executed, the processor reads the data from the following sequence of Hex addresses.

200 , 204 , 208 , 20C , 2F4 , 2 F0 , 200 , 204 , 218 , 21C , 24C , 2 F4 . The Pattern is repeated 4 times. Assume that the cache is initially empty, show the contents of the cache at the end of each pass, and compute the hit rate for a direct mapped cache

23. Discuss the various mapping schemes used in cache design. Compare the schemes in terms of cost and performance. Consider the total level cache with access time of 5 ns, and 80 ns respectively. If the hit rate is 95% and 75 % respectively in the 2 caches, and memory access time is 250 ms, what is the average access time?

UNIT V - I/O ORGANIZATION

2 MARKS

UNIVERSITY QUESTIONS

1. List out the types of interrupt.

2. What is DMA?

3. Distinguish between horizontal and vertical microprogramming organizations.

4. Discuss the typical features of an IO processor.

5. Differentiate Isolated I/O from Memory mapped I/O.

6. What are the different modes of I/O transfer available?

7. List the different types of interrupts. Explain briefly about maskable interrupt.

8. Write about memory mapped I/O and I/O mapped I/O.

9. Distinguish between a synchronous bus and an asynchronous bus.

10. How does a processor handle an interrupt?

11. What are the functions of a typical I/O interface?

12. How does the processor handle an interrupt request?

13. How are multiprocessors classified based on their memory organization?

14. Consider a computer in which several devices are connected to a common interrupt request line.Explain how you would arrange for interrupts from device j to be accepted before the execution of the interrupt service routine for device i is completed. Comment in particular on the times at which interrupts must be enabled and disabled at various points in the system.

15. How do you differentiate the inter and intra system communication?

16. When DMA and interrupt are processed by CPU?

17. What is the advantage of using interrupt initiated data transfer over transfer under program control without interrupt?

18. Why are interrupt masks provided in any processor?

19. How does bus arbitration typically work?

20. What are the two major advantages and disadvantages of the bus?

16 MARKS

UNIVERSITY QUESTIONS

1. Describe the data transfer method using DMA.

2. Write short notes on Magnetic disk drive and optical drives.

3. What are the different ways in which data can be transferred between the processor and the peripheral devices? Point out the relative merits and demerits of these schemes. What is DMA controller? Show how a typical DMA transfer is accomplished?

4. Explain I/O processor with an example. Write notes on vectored interrupts.

5. Explain the DMA mode of I/O transfer in detail.

6. Explain the following data transfer schemes with necessary diagrams; interrupt driven Data transfer and DMA data transfer.

7. Discuss in detail the various forms of input devices used.

8. What is a DMA transfer? Explain in detail how it is accomplished. Distinguish between memory mapped I/O and I/O mapped I/O

9. Discuss the design of a typical input / output interface.

10. What is DMA Transfer? How does it take place? Write short note on the functionalities carried out by an I/O processor?

11. Discuss the different types of interrupts. How does a processor handle them? Distinguish between synchronous and asynchronous bus transfers.

12. What are the functions to be performed by a typical I/O interface? Explain the interrupt driven mode of data transfer and the DMA driven data transfer elaborating on how they are accomplished and their relative merits and demerits

13. Distinguish between synchronous and asynchronous bus transfers. Discuss the storing, organization and accessing of data in a magnetic hard disk.

14. Explain about PCI and pipeline interrupts. Write briefly about interrupt and discuss the various scheme used to select interrupt.

15. Design parallel priority interrupt hardware for a system with 8 interrupt sources. Describe the functions of SCSI with a neat diagram.

16. What is the importance of an I/O interface? Compare the features of SCSI and PCI interfaces. What are the different input and output signals of DMA controller? Why are the read and write control signals are bidirectional? Under what condition and for what purpose they are used as inputs and outputs?

17. Explain the use of vectored interrupts in processors .Why is priority handling desired in interrupt controllers? How do the different priority schemes work? Discuss the data transfer mechanism of the PCI bus.

18. Explain how data may be transferred from a hard disk to memory using DMA including arbitration for the bus. Assume a synchronous bus, and draw a timing diagram showing the data transfer, Discuss the salient features of the USB operation.

19. Explain the functions to be performed by a typical I/O interface with a typical input or output interface.

20. Discuss the DMA driven data transfer technique. Discuss the operation of any 2 input devices.

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