Part I:



Senior Design Project P6505:

Multi-channel Biomedical Data Acquisition System

Preliminary Design Report

Members: Jim Massaro, Charles Spuckler, and Matthew Huff

Sponsor / Advisor / Coordinator: Dr. Daniel Phillips

11 November 2005

Introduction

Approximately 1% of the world population suffers from epilepsy, a “chronic neurological condition characterized by recurrent unprovoked seizures” (Wikipedia). Of this group, less than 50% have a detectable cause for the condition, and 25% cannot be controlled using common methods such as taking medication or having a surgical procedure. This leads to the search for a way to identify when a seizure will occur, so that the epileptic can ensure their own safety and the safety of others around them when the seizure happens. One method currently being researched to predict a seizure is to utilize electroencephalogram (EEG) signals, which show brain wave activity, that have been analyzed to look for patterns that precede a seizure. This is where this particular senior design project begins, with the acquisition and conversion of EEG signals for use in analyzing and predicting epileptic seizures.

Project Overview

The general scope of this project is to create an MCU based embedded data acquisition and processing system that will receive multiple analog EEG signals, filter and digitize the incoming signals, process and encode the data in a specified format, and then transmit the data to a signal processing system. The output of the system will be on a standard communication link and protocol that will allow transfer to the primary source (a multiple DSP based processing system), and then optionally to a personal computer for storage. A simple block diagram depicting the basic data flow just described is presented in Figure 1.

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Figure 1: Basic data flow into and out of multi-channel biomedical data acquisition system as proposed.

Project Rationale

Initially, the rationale behind the project request needed to be ascertained. For the functionality just described in the project overview, all that would really be required for a minimum of hardware would be a DSP chip with the capability to convert the analog signals to digital before processing the data. While this option sounds simple to implement, and DSP chips with integrated ADC hardware are not unheard of, the actual logistics of receiving all of the signals to be sampled, converting the data, and then processing the result would be a huge task for the DSP. It should also be noted that the DSP, aptly named, is optimized for digital signal processing, not necessarily the sampling and acquisition of the data. For these reasons, a system that takes care of the data acquisition and then packages the data for quick access by the DSP is beneficial. Besides simply being able to accompany a DSP, this system will also have value as a means of allowing digital outputs to be available for an otherwise purely analog EEG machine. The final reason behind this particular project is that this is only the first in a sequence of projects that will culminate in a system, as described in the introduction, to sample EEG signals, digitally process the data in real time, and be used to predict the onset of an epileptic seizure.

Requirements

Once the basic premise of the multi-channel biomedical data acquisition system (MCBDAS) was understood, more details on how the system would operate were required. After the initial meeting with the sponsor, a list of requirements was created to guide the design process. This list follows:

• Sampling rate and digital bit resolution such that data can be considered synchronous and accurate: required to be at least 1 kHz and 12 bits

• Process and transmit up to 23 analog EEG signals in one sampling period

• Filter signal noise between EEG machine and system without modifying original signal

• Error checking capability for data transmitted

• Serial output connection compatible Texas Instruments DSP McBSP serial communication protocol

• System calibration command available to user

• System electrically isolated from all peripherals to ensure user and patient safety

• Apply known inputs signals and test output for accuracy

• Overall price of system not to exceed $1000

These requirements were then submitted for approval by the sponsor, effectively documenting that both the sponsor and the team were in agreement on what the system would need to successfully accomplish. This document is provided in the team binder under the Requirements tab.

Initial Design Phase

With the requirements of the MCBDAS agreed upon, an initial design could be made to help in the creation of system specifications. Each team member took the requirements and came up with a system design that would meet them. For this basic design, only functionality would be the focus, not individual part choices or other unnecessary details at this point. One such design is shown in Figure 2.

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Figure 2: Multiple microcontroller system design concept diagram.

The basic premise of this design was to utilize the built in ADC function common in most microcontrollers (MCU’s), and in doing so avoid the addition of extra components to the system. With 23 input signals to the system, and knowing that some MCU’s have up to 12 or more analog to digital converter (ADC) channels available, only two MCU’s would be needed for the conversion of the 23 signals, and a third MCU would be used as the system controller, controlling the operation of the two MCU’s, receiving the converted data, and sending the data out to the DSP. While this design does allow for less variety in required components, it also has a number of drawbacks. One major drawback is the resolution on nearly all MCU ADC’s is limited to 12 bits, which at this point was being decided would be a variable in the final version of the system. Also of note is the increased amount of programming required, nearly three times the code required in a single MCU system. In a quick feasibility assessment, this design was discarded as an inefficient method to accomplish the requirements. Another design that ranked more favorably with the team is shown in Figure 3.

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Figure 3: Dedicated ADC and MUX system design concept diagram.

This design relied on a dedicated ADC chip to perform the conversion, passed each input through an individual filter and sample/hold circuit, and used a multiplexer (MUX) to select each channel for conversion in sequence, with a single MCU to control the system and output the data. The major active components, including the MCU, ADC, MUX, and filters were all connected to form the data path through the system, and required control lines were also accounted for. At this point in the design, synchronous data acquisition was also a key component, requiring the sample/hold circuits to make sure all of the incoming signals were sampled at the same instant in time each sampling period. Between conception of this design and creation of specifications, the sponsor decided that the system did not have to be synchronous, instead simply allowing for a small delay between samples. With this new modified requirement, the sample/hold circuits would no longer be needed as long as the ADC chip was fast enough in converting so that the time between signal sampling was negligible. With this new knowledge, and with feedback from the sponsor on the basic system design of Figure 3, the basic version of the final design was created, as shown in Figure 4.

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Figure 4: Basic functionality diagram of final system design.

In moving from the design of Figure 3 to Figure 4, major issues with the number of components in the system were addressed. In removing the requirement that the data be strictly sampled synchronously, the need for each signal to be passed through a sample and hold circuit was removed. This allowed for the signal selecting MUX to be placed first in the system data path order, leading to a single path the rest of the way through the system, which simplified the design immensely. The filtering of the signals, which by this point in the project development had started to become a major issue, was decided to be matched to the sampling frequency, which also at this point was being set as a user-determined variable to the system. This required that the individual signal being passed through the system be filtered through each separate filter available, and then the output of the correct filter for the set sampling frequency would be chosen. This lead to the need for a second MUX in the system, to select the correct filter output for conversion by the ADC. The rest of the system was unchanged, and with this final design in hand and approved by the sponsor, system specifications could finally begin to be determined.

Specifications

By using both the requirements displayed earlier and the design just presented, specifications for the MCBDAS were created. In making sure that all required values were met, and integrating the suggested variables brought up in weekly team meetings with the sponsor / advisor, the specifications list show below, which is split into major categories and responsibilities of the system, was produced.

Sampling: The sampling of the proposed system will be variable between 1000 Hz, as was required, 500 Hz, and 200 Hz. These three values were chosen to allow the user to decide at what rate the required data should be collected and transmitted. Also of importance in this decision was the fact that EEG output signals generally range from 30 – 80 Hz, which enters into the filtering design that in turn is also impacted by the sampling frequency.

Resolution: A range of resolutions will be available for the transmitted digital signals from the system, including 16, 14, 12, 10, and 8 bits. This will allow a maximum voltage resolution of 198 µV and a minimum of 50.8 mV for input signal range of ±6.5 V, as specified by the level of the EEG output signals.

Input: A total of 23 analog input signals with voltage ranges of ±6.5 V will be accepted by the system. This is mandated by both the number of and voltage range of the outputs of the EEG machine provided by the sponsor. Individual stereo plug cables will be used to connect EEG machine outputs to inputs of system.

Output: A serial output line will be used by the system both for transmission of digitized EEG signals and for reception of command string from DSP to set up variables in system and to control operation. McBSP protocol will be used as communication method on serial connection, and commands to system will include: start converting, stop converting, status of system, calibrate. The actual rate of transmission between the system and the DSP has yet to be determined, since no information has been received on the particular DSP to be used. This is required information since the McBSP transmit rate, which can reach a maximum of 70 Mbps, is entirely dependant on the speed capability of each device using the connection.

Filtering: For the 1000 Hz sampling rate a cut-off frequency of 120 Hz with 100 dB of attenuation at the Nyquist rate of 500 Hz. For the 500 Hz sampling rate a cut-off frequency of 70 Hz with 100 dB of attenuation at the Nyquist rate of 250 Hz. For the 200 Hz sampling rate a cut-off frequency of 35 Hz with 100 dB of attenuation at the Nyquist rate of 100 Hz.

Data Format: Transmitted data will be in format containing header, signal data transmitted, and an error checking mechanism. User will define both number and order of output signals in initial command string sent to start system into conversion.

Power: Power supply will be isolated from both inputs and outputs of system. Supply will be able to supply all voltage levels and corresponding current values for entire system from single 120 VAC input that user will plug into common power outlet. LED mounted on system enclosure will indicate that power is successfully supplied to system.

Error Checking: System will utilize DC voltage level from power supply to act as known value for calibration source. Calibration will include passing calibrate signal through system and checking output against expected value. Error will be indicated both through output response to calibrate command from DSP and through LED indicator mounted on system enclosure.

EEG Specifications

The EEG is capable of taking cerebral measurements or ECG measurements, with frequency range from >0 to 70 Hz and >0 to 100 Hz, respectively. The amplitude of these signals is about 50 µV and is measured differentially using high precision instrumentation amplifiers with CMRR > 10,000. The CMRR is the ability of the amplifier to successfully differentiate the two signals. This can be seen in Figure 5. For the Nihon Kohden these signals are amplified to an output of 1 V. This computes to a gain of 20,000 V/V. Because of this high gain the anti-aliasing filters that are to be designed must have no ripple in the pass-band for successful reconstruction.

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Figure 5: Schematic showing EEG signals received from electrode on patient.

The frequency response of the EEG is a low-pass filter in series with a high-pass filter, with frequency response HLP(jw) and HHP(jw), respectively. Therefore the frequency response of the system is given as

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where k is the gain. The high-pass filter has adjustable cut-off frequencies of 0.1 Hz, 0.5 Hz, 1 Hz, and 5 Hz. The low-pass filter has adjustable cut-off frequencies of 15 Hz, 35 Hz, 70 Hz, and 120 Hz. This leads to the design specifications of the anti-aliasing filters to be built. 1000 Hz sampling corresponds to a cut-off frequency of 120 Hz, 500 Hz sampling corresponds to a cut-off frequency of 70 Hz, and 200 Hz sampling corresponds of a cut-off frequency of 35 Hz. The highest cut-off frequency is chosen for the highest sampling rate because this makes the filter a lower order and easier to build in hardware.

Project Timeline

Up to this point, the rough Gantt chart created in the initial design phase was fairly incomplete, since not enough information was known about the system to accurately predict how much time would be needed to be spent on each individual aspect, or even what specific events would need to be completed. However, with the design and specifications just covered, a more detailed timeline was created to assist in making sure the project progressed at an acceptable pace and all major deadlines were met. A chart with the combined initial timeline and the more specific system component Gantt chart is shown in Table 1.

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Table 1: Rough Gantt chart for team tasks during Senior Design I

Along with the Gantt chart, which was a tool used in meeting team deadlines, a general work distribution within the group was decided. In having already read a bit of the EEG machine manual, Jim was chosen as the EEG information specialist of the group. The filtering, which is a major issue since it is one of the few system components to be designed and built entirely by the group, was decided to be a joint effort between Jim and Charles. As for coding experience, neither Jim nor Charles had much, and so Matt was chosen as the MCU programmer and information specialist. Almost a companion to the MCU portion, the McBSP protocol, which no one, not even the sponsor / advisor, was familiar with, was also conferred as a responsibility of Matt’s. As the final product of this senior design project is expected to be a printed circuit board (PCB) as opposed to a bread board, one of the group members would have to become familiar with PCB layout software. This duty was given to Charles. All other tasks that needed accomplished would either be done by the group, or would be assigned to a group member not immediately busy with other individual tasks. With these guidelines set up, expanding on and finalizing the MCBDAS design could be accomplished.

Final Design Description

The basic block diagram for the design of the MCBDAS is shown in Figure 6.

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Figure 6: Block diagram of final system design showing data flow and control signals.

The system takes the EEG source analog signals then multiplexes them. The chosen input is sent through the appropriate anti-aliasing filter. The signals are then sampled and held in sample and hold circuit. After being sampled, the signal is converted by the analog to digital converter. The microcontroller receives the outputs analog to digital converter. The microcontroller stores the data and then adjusts the control lines to the multiplexer so that the next input can be converted. After all the inputs have been converted, the system then prepares the data for transmitting to the DSP chip. This preparation includes adding header information about the data being sent and error checking information.

The microcontroller is able to send and receive data from the DSP. The DSP will be able to tell the microcontroller the wanted sampling frequency and bit resolution. The DSP will also tell the microcontroller which lines to sample and in which order. This order will determine which control lines of the multiplexer gets activated. The sampling frequency will determine when sampling occurs and which anti-aliasing filter is used. The microcontroller will be capable of adjusting the bit resolution of the sampled signal. This will be done by discarding unwanted bits.

The communication between the DSP and microcontroller will be done through the McBSP protocol for communication, produced by TI. This method was chosen since is supported by the DSP and is capable of supporting amount of data that is being transmitted.

The microcontroller is also able to send out error information about the state of the system. The list of errors includes bad setup commands. The setup commands deal with setting which lines to sample and the order to sample the lines, bit resolution, and sampling frequency. Other commands will tell the system to start converting data and sending data. Another command will tell the system to stop conversion and sending data. There will also be a command to tell the system to use the calibration signal.

This design features one sample and hold and one set of anti-aliasing filters. Another possible design consideration was to sample and hold and filter before the multiplexer. This design would require that each input have its own sample and hold and anti-aliasing system. This design would allow for samples from each line to be taken from the same time. This design would be require a large amount of components that could be costly. With the current design, there will be a small amount of delay between the first and last samples taken. This delay will be small compared to the sampling period.

Final Design Component Details

Figure 7 shows the more detailed version of the final design. It features the inclusion of specific control and power lines to each component. It also features the individual part numbers that have been picked out for use in the system.

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Figure 7: Detailed version of final design showing power connections and actual part specific pin connections.

The power supply, NFS40-7908, of the system was chosen to be a medical power supply. This power supply can produce the needed -12V, +12V and 5V needed by the system. The power supply is also isolated, a requirement in the biomedical application. Isolation should help to protect the person connected the EEG machine and as well as the components of the machine. This power supply will provide enough power to all parts of the system as shown by the following feasibility summary of Table 2.

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Table 2: Power supply feasibility used to attain required power for system from individual power draw of components.

The input multiplexer of the system was changed to two 16 input multiplexers, ADG406. The 16 input multiplexers have the needed voltage range of +/-6.5. The multiplexers also have fast switching time of 150ns and work well with the frequencies that it is dealing with. The control lines of the multiplexer are connected to the same I/O pins of the microcontroller controller. Only one will be active at a time due to the inverting of the enable line to one of the multiplexers. Two multiplexers were used due the unavailability of 32 input multiplexers with the needed voltage range.

The anti-aliasing filters have cutoff frequencies that correspond to cutoff frequencies of the filters within the EEG. 35Hz is the cutoff frequency for the filter used when sampling at 200 Hz. 70Hz is the cutoff frequency for the filter used when sampling at 500 Hz. 120Hz is the cutoff frequency for the filter used when sampling at 1000 Hz. Using an adjustable anti-aliasing filter was also considered. Adjusting a filter would require changing a large number of components or using a switch capacitor filter. Changing a large number of components would add greatly to the complexity of the system compared to using 3 fixed filters. The switch capacitor filter would require a clock signal for each of the different sampling times and lack the needed attenuation requirements.

The 3 anti-aliasing filters were designed. Each filter has an attenuation of 100dB at half the sampling frequency. This amount of attenuation was determined by the formula 20*log (3.5*2B). In this formula, B represents the bit resolution in the ADC. This formula resulted from need that the maximum voltage range of the ADC, Vmax, needs to be reduced to levels within a bit after conversion, VMAX/2B. An extra factor of 3.5 will further reduce the signal to smaller voltages. This amount of attenuation should prevent aliasing to have a noticeable effect on the signals after the digital conversion have taken place.

Different types of filters were examined to due the filtering. The elliptical and the Chebyshev both feature ripples in the pass band. The allowable ripple was determined by the equation VMAX*x=VMAX –VMAX/2B. This will prevent the ripple attenuation from changing more then one bit. The allowable ripple attenuation, x, was determined to be 20*log(1-1/2B) or 132e-6 dB for a 16 bit ADC. The Butterworth would provide a flat response to the filter. The Butterworth filter also has a better phase response and group delay when compared to the Chebyshev filters. For these reasons, a Butterworth filter was used.

The circuit implementation of the Butterworth for 200 Hz is shown in Figure 8. The simulated frequency response is plotted in Figure 9. The capacitor values will need to be adjusted to standard capacitor values. The Sallen-Key filter was used due to its ability to construct 2 poles with a 1 op amp.

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Figure 8: Simulation schematic for Butterworth filter at 200Hz sampling rate

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Figure 9: Frequency response for the 200Hz sampling rate filter shown in Figure 7

The multiplexer, ADG409, allows the output of the filter with the appropriate cutoff frequency through. This multiplexer also have the need output voltage range, +/- 6.5V, and a quick switching time, less then150ns. The output of this multiplexer will go into the ADC. The control lines of the MUX are controlled by the microcontroller.

The analog to digital converter, ADS7805, was chosen based on its speed 10µs and its built in sample and hold capabilities. The analog to digital converter also has the needed 16 bit resolution. The speed of the analog to digital converter enables it go through the sampling of the all the different inputs quickly enough that time difference between the first and last samples taken is small. The sampling part of the system also needs to be done fast enough that the microcontroller has enough time to format the data and send it to the DSP. The ADC also has parallel output, which go into the microcontroller. The command lines to ADC will tell when to convert. The ADC sends a signal telling the microcontroller that a conversion is in progress.

The microcontroller, PIC18F4550, was chosen based on its speed, 48 MHz, and other characteristics. The microcontroller has enough control lines, 34, that it can take the parallel output of the analog to digital converter. The microcontroller is also able to sample all the different lines and send out the data within the smallest sampling period, which is 1ms. The USB interface of the microcontroller will allow for programming and debugging of the system while the microcontroller is in the system. This is likely to spend up development of the system. The microcontroller has 2 Kbytes of RAM to hold up to 23, 16 bit signals, error codes, and headers. The microcontroller controls the multiplexers and the ADC and receives commands from the DSP.

There this also a calibration signal included in the system. This signal will be a 5 VDC signal. This signal will come from the power supply. A calibration signal of 5 V was chosen to match the calibration signal of the EEG.

Testing Procedures

The following describes how each component individually will be checked for correct operation in Senior Design II.

Micro-Processor

The micro-processor software will be designed and tested using the PICDEM Full Speed USB demo kit. This will be supplied by Microchip. A DSP will be provided to simulate the communication link between the DSP and MCU. The output of the DSP can be viewed on the computer development software provided by Texas Instruments. The DSP software is unknown and experience must be gained before implemented.

Multiplexer

The MCU and multiplexer sampling must be tested to ensure that the data is sampled in the correct order.

Filters

The three analog filters are designed for cut-off frequencies of 35 Hz, 70 Hz, and 120 Hz for sampling rates of 200 Hz, 500 Hz, and 1000Hz, respectively. The response of each filter will be simulated in PSPICE then tested on a breadboard with an oscilloscope, a power supply, and a signal generator. The transient step response from the hardware will then be compared to the transient step response of the simulated results and the calculated results. In hardware, the signal generator input frequency can be varied to test the filter’s attenuation from the pass band to the stop band. The output should be attenuated as per the design specifications and the simulations. The response should also be tested with the output impedance of the EEG as to not degrade the signal.

Analog to Digital Converter

The ADC will be tested separately from the rest of the components using a power supply as a controlled input. The output will be connected to the MCU demo kit to see if the values are accurate. The ADC comes in a DIP package, so a breadboard can be used to connect the ADC I/Os to the MCU. An oscilloscope will be connected between the input of the ADC and the supply to verify the signal. The MCU software can view the input from the ADC as a digitized signal. Since the ADC is a critical element of the design, it should be tested for noise immunity and conversion rate.

System Assembly

Once each component is tested and verified the system can be assembled. The system will be assembled on a PCB. A rough timing diagram has been constructed to view the flow of data. This can be seen in Figure 10. Before the timing diagram can be complete the delay of the anti-aliasing filter must be found. Then a scaled version of the diagram can be constructed.

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Figure 10: Rough system timing diagram showing control signals to components and active period with signal.

Use of the timing diagram will be important to ensure accurate sampling of each channel in the specified sample period.

EEG Compatibility

Once each component of the system is tested and verified in simulation and hardware, the system can be assembled and tested with the output of the EEG. The EEG is capable of taking in 23 DC inputs, and processing the signals through the external output. This would verify that the signal from the EEG is not degraded through our system. The testing diagram for the EEG system is shown in Figure 11.

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Figure 11: Block diagram of EEG testing procedure.

System Bill of Materials

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Table 3: Bill of materials for the proposed MCBDAS with number of parts to be ordered for each component.

Future Timeline and Work Distribution

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Table 4: Gantt chart for anticipated actions during Senior Design II in spring quarter of 2006.

The responsibilities for testing and integration for Senior Design II will be as follows:

Charles Spuckler

1) Simulation of filters

2) Gain experience with PCB software and integration

3) Hardware Design and test of filters

4) System integration testing with EEG

Matthew Huff

1) ADC and MCU software design and integration

2) Testing MCU with sampling MUX

3) System integration testing with EEG

Jim Massaro

1) Gain experience with DSP software

2) System integration testing with EEG

3) Hardware Design and test of filters

References







Van Valkenburg, M.E. Analog Filter Design, Oxford University Press, New York, 1982.

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