Cse2a
COURSE/SUBJECT FILE
For
DIGITAL LOGIC DESIGN
Course file contents
Cover Page
Syllabus copy
Vision of the Department
Mission of the Department
PEOs and POs
Course objectives and outcomes
Brief notes on the importance of the course and how it fits into the curriculum
Prerequisites if any
Instructional Learning Outcomes
Course mapping with POs
Class Time Table
Individual time Table
Lecture schedule with methodology being used/adopted
Detailed notes
Additional topics
University Question papers of previous years
Question Bank
Assignment Questions
Unit wise Quiz Questions and long answer questions
Tutorial problems
Known gaps ,if any and inclusion of the same in lecture schedule
Discussion topics , if any
References, Journals, websites and E-links if any
Quality Measurement Sheets
Course End Survey
Teaching Evaluation
Student List
Group-Wise students list for discussion topics
Course coordinator HOD
|Geethanjali College of Engineering and Technology |
|DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING |
|(Name of the Subject/Lab Course): DIGITAL LOGIC DESIGN |
|(JNTU CODE: A30401) Programme: UG |
|Branch: CSE Version No: 1 |
|Year: II A & B Document Number :GCET/CSE/ |
|Semester: I No. of Pages: |
|Classification status (Unrestricted/Restricted ) : Unrestricted |
|Distribution List: Unrestricted |
|Prepared by : | |
|1) Name : D.VENKATESWARLU |1) Name : M. VIJAY BHASKER REDDY |
|2) Sign : | |
|3) Design : ASSOCIATE PROFESSOR |2) Sign : |
|4) Date : 26-05-2016 |3) Design : ASSISTANT PROFESSOR |
| |4) Date : 26-05-2016 |
|Verified by : *For Q.C only |
|1) Name : 1)Name : |
|2) Sign : 2) Sign : |
|3) Design : 3) Design : |
|4) Date : 4) Date : |
|Approved by (HOD) : |
|1) Name : |
|2) Sign : |
|3) Date : |
2. JNTU Syllabus
DIGITAL LOGIC DESIGN( II Year B.Tech. CSE-I Sem)
UNIT-I
Digital Systems: Binary Numbers, Octal, Hexa Decimal and other base numbers, Number base conversions, complements, signed binary numbers, Floating point number representation, binary codes, error detecting and correcting codes, digital logic gates(AND, NAND,OR,NOR, Ex-OR, Ex-NOR), Boolean algebra , basic theorems and properties, Boolean functions, canonical and standard forms.
UNIT-II
Gate –Level Minimization and combination circuits , The K-Maps Methods, Three Variable, Four Variable, Five Variable , sum of products , product of sums Simplification, Don’t care conditions , NAND and NOR implementation and other two level implantation.
UNIT-III
Combinational Circuits (CC): Design Procedure, Combinational circuit for different code converters and other problems, Binary Adder, sub-tractor, Multiplier, Magnitude Comparator, Decoders, Encoders, Multiplexers, De-multiplexers.
UNIT-IV
Synchronous Sequential Circuits: Latches, Flip-flops, analysis of clocked sequential circuits, design of counters, Up-down counters, Ripple counters , Registers, Shift registers, Synchronous Counters. Asynchronous Sequential Circuits: Reduction of state and follow tables, Role free Conditions.
UNIT-V:
Memory: Random Access memory, types of ROM, Memory decoding, address and data bus,
Sequential Memory, Cache Memory, Programmable Logic Arrays, memory Hierarchy in terms of capacity and access time.
.
3.Vision of the Department
To produce globally competent and socially responsible computer science engineers contributing to the advancement of engineering and technology which involves creativity and innovation by providing excellent learning environment with world class facilities.
4 Mission of the Department
To be a center of excellence in instruction, innovation in research and scholarship, and service to the stake holders, the profession, and the public.
To prepare graduates to enter a rapidly changing field as a competent computer science engineer.
To prepare graduate capable in all phases of software development, possess a firm understanding of hardware technologies, have the strong mathematical background necessary for scientific computing, and be sufficiently well versed in general theory to allow growth within the discipline as it advances.
To prepare graduates to assume leadership roles by possessing good communication skills, the ability to work effectively as team members, and an appreciation for their social and ethical responsibility in a global setting.
5.PROGRAM EDUCATIONAL OBJECTIVES (PEOs) OF C.S.E. DEPARTMENT
To provide graduates with a good foundation in mathematics, sciences and engineering fundamentals required to solve engineering problems that will facilitate them to find employment in industry and / or to pursue postgraduate studies with an appreciation for lifelong learning.
To provide graduates with analytical and problem solving skills to design algorithms, other hardware / software systems, and inculcate professional ethics, inter-personal skills to work in a multi-cultural team.
To facilitate graduates to get familiarized with the art software / hardware tools, imbibing creativity and innovation that would enable them to develop cutting-edge technologies of multi-disciplinary nature for societal development.
\
PROGRAM OUTCOMES (CSE)
Program Outcomes
Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization to the solution of complex engineering problems.
Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences.
Design/development of solutions : Design solutions for complex engineering problems and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations.
Conduct investigations of complex problems: Use research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions.
Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and modeling to complex engineering activities with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice.
Environment and sustainability: Understand the impact of the professional engineering solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice.
Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings.
Communication: Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions.
Project management and finance: Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments.
Life-long learning : Recognize the need for, and have the preparation and ability to engage in independent and life-long learning in the broadest context of technological change.
6. Objectives and Out comes
Course Objectives:
To understand basic number systems codes and logical gates.
To understand the Boolean algebra and minimization logic.
To understand the design of combinational and sequential circuits to improve the efficiency of the hardware and software systems.
To understand the basics of various memory systems, memory internal organizations and representations
To understand Memory speed accessing mechanisms.
Outcomes:
C204.1:- After this course students could able to do with number systems and codes and their application to digital circuits.
C204.2:- Could able to do with fundamentals of Boolean algebra and theorems, K-maps including minimization of logic functions to SOP or POS forms.
C204.3:- Could able to do with mathematical characteristics of logical gates. and how to use truth tables, boolean algebra, K-maps, and other methods to obtain design equations.
C204.4:- Learn how to use design equations and procedures to design the combinational and sequential systems consisting of gates and flip-flops.
C204.5:- Could know the basic s of various memory techniques.
C204.6:- And they should be in a position to continue with computer organization.
7 Brief notes on the importance of the course and how it fits into the curriculum
Students can do with number systems and codes and their application to digital circuits.
To know the fundamentals of Boolean algebra and theorems, K-maps including minimization of logic functions to SOP or POS forms.
Students can do with mathematical characteristics of logical gates.
Learning how to use truth tables, Boolean algebra, K-maps, and other methods to obtain design equations.
Learning how to use design equations and procedures to design the combinational and sequential systems consisting of gates and flip-flops.
Combining combinational circuits and flip-flops to design combinational and sequential systems.
Students can do with basic s of various memory.
Scope
The purpose of this course is that we:
Learn what’s under the hood of an electronic component
Learn the principles of digital design
Learn to systematically debug increasingly complex designs
Design and build a digital system
8. Prerequisites
Boolean minimization
Combinational networks design.
Sequential networks design.
Karnaugh map.
9 . Instructional Learning Outcomes
Students can do with number systems and codes and their application to digital circuits.
To know the fundamentals of Boolean algebra and theorems, K-maps including minimization of logic functions to SOP or POS forms.
Students can do with mathematical characteristics of logical gates.
Learning how to use truth tables, Boolean algebra, K-maps, and other methods to obtain design equations.
Learning how to use design equations and procedures to design the combinational and sequential systems consisting of gates and flip-flops.
Combining combinational circuits and flip-flops to design combinational and sequential systems.
Students can do with basic s of various memory.
Scope
The purpose of this course is that we:
Learn what’s under the hood of an electronic component
Learn the principles of digital design
Learn to systematically debug increasingly complex designs
Design and build a digital system
10. DLD COURSE MAPPING WITH PEOs AND POs
Mapping of Course with Programme Educational Objectives
|S.No |Course |code |Semester |PEO 1 |PEO 2 |PEO 3 |
|1 |DLD | |I |√ |√ |- |
Mapping of Course outcomes with Programme outcomes:
*When the course outcome weightage is < 40%, it will be given as moderately correlated (L).
*When the course outcome weightage is >40 &< 60%, it will be given as moderately correlated (M).
*When the course outcome weightage is >60%, it will be given as strongly correlated (H).
|POs |1 |2 |3 |4 |
|1 |1 |Digital Systems, Binary Numbers |Regular |BB |
|2 | |Number base conversions, Octal |Regular |BB |
| | |and Hexadecimal Numbers and | | |
| | |Other base conversions | | |
|3 | |Complements, Signed binary numbers |Regular |BB |
|4 | |Floating point representations |Regular |BB |
| | |Binary codes | | |
| | |Assignment test on unit-1 | | |
| | |Error detecting and correcting | | |
|5 | |Binary Storage and Registers, Binary logic |Regular |BB |
|6 | |Conversion from gray code to other codes |Additional |BB |
|7 | |Tutorial class on unit-1 | | |
| | |Digital Logic Gates(AND,NAND,OR,Ex-OR,Ex-NOR ect.,) | | |
|8 | |Boolean Algebra and– Basic Definitions, Axiomatic definition of Boolean |Regular |BB |
| | |Algebra | | |
|9 | |Basic theorems and properties of Boolean algebra |Regular |BB |
|10 | | Boolean functions |Regular |BB |
| | |canonical and standard forms | | |
|13 | |Tutorial class on unit-1 | | |
|14 | |Assignment test on unit-1 | | |
| | | | | |
|15 |2 |Gate level minimization – The map method |Regular |BB |
|16 | |three-Variable ,Four-variable and Five-Variable maps. |Regular |BB |
|17 | |Assignment test on unit-2 | | |
|18 | |Six-variable map |Additional |BB |
|19 | |Product of sums simplification |Regular |BB |
|20 | |Sum of product simplification, Don’t-care conditions |Regular |BB |
|21 | |NAND and NOR implementation |Regular |BB |
|22 | |Assignment test on unit-2 | | |
|23 | |other Two-level implementations: AND–OR–INVERT Implementation, and |Regular |BB |
|24 | |OR-AND-INVERT Implementation. |Regular |BB |
|25 | |Tutorial class on unit-2 | | |
| | | | | |
|26 |3 |Combinational Circuits, Analysis procedure Design procedure |Regular |BB |
|27 | |Combinational circuits for different code conversion(BCD to excess-3 code) |Regular |BB |
|28 | |Multiplier |Regular |BB |
|29 | |Binary Adder- Subtractor(half, full & binary adder) |Regular |BB |
|30 | |Decimal Adder(BCD Adder) |Regular |BB |
|31 | |Binary multiplier, Magnitude comparator |Regular |BB |
|32 | |Decoders |Regular |BB |
|33 | |Encoders |Regular |BB |
|34 | |Multiplexers and De-Multiplexers |Regular |BB |
|35 | |Tutorial class on unit-3 | | |
|36 | |Assignment test on unit-3 | | |
|37 | | | | |
|38 |4 |Sequential circuits: ; |Regular |BB |
|39 | |latches(storage elements):SR and D-Latches |Regular |BB |
|40 | |Flip-Flops: Edge Trigger D-flip flop |Regular |BB |
|41 | |SR,JK,D and T-Flip-Flops |Regular |BB |
|42 | |Assignment test on unit-4 | | |
|43 | |Analysis of clocked sequential circuits |Regular |BB |
|44 | |Design of counter: Ripple counter : |Regular |BB |
|45 | |Binary ripple counter, BCD Ripple counter and |Regular |BB |
|46 | |Synchronous circuits :binary counter and |Regular |BB |
|47 | |Up-Down binary counter |Regular |BB |
|48 | |Asynchronous sequential circuits |Regular |BB |
|49 | |Other counter : Ring and Johnson counters |Additional |BB |
|50 | |Registers: Register with parallel load, |Regular |BB |
|51 | |Shift registers: serial transfer and serial adder and |Regular |BB |
|52 | |Universal shift register |Regular |BB |
|53 | |Reduction of state and follow table |Regular |BB |
|54 | |Role free conditions |Regular |BB |
|55 | |Tutorial class on unit-4 | | |
|56 | | | | |
|57 |5 |Introduction to memory systems. Random-Access Memory |Regular |BB |
|58 | |Types of memories : RAM and ROM. Types of ROMs |Regular |BB |
|59 | |Address and data bus |Regular |BB |
|60 | |Memory Decoding |Regular |BB |
|61 | |Programmable logic Array, and |Regular |BB |
|62 | |programmable Array logic |Regular |BB |
|64 | |Hierarchy of memory in terms of capacity and access time |Regular |BB |
|65 | |Tutorial class on unit-5 | | |
Lecture Schedule with expected dates
II Year B.Tech. CSE-I Sem A-Section Faculty: M Vijay Bhasker Reddy w.e.f: 13/06/2016
|SL. |Unit No |Topic to be covered in One lecture |Expected dates |Teaching aids used |
|No | | | |LCD/OHP/BB |
|1 |1 |Digital Systems, Binary Numbers |13/06/2016 |BB |
|2 | |Number base conversions, Octal |14/06/2016 |BB |
| | |and Hexadecimal Numbers and | | |
|3 | |Other base conversions |14/06/2016 | |
|4 | |Complements, Signed binary numbers |17/06/2016 |BB |
|5 | |Tutorial |18/06/2016 | |
|6 | |Floating point representations |20/06/2016 | |
|7 | |Binary codes |21/06/2016 | |
|8 | |Error detecting and correcting |21/06/2016 | |
|9 | |Binary Storage and Registers, Binary logic |24/06/2016 |BB |
|10 | |Conversion from gray code to other codes |25/06/2016 |BB |
|11 | |Tutorial class on unit-1 |27/06/2016 | |
|12 | |Digital Logic Gates(AND,NAND,OR,Ex-OR,Ex-NOR ect.,) |28/06/2016 | |
|13 | |Boolean Algebra and– Basic Definitions, Axiomatic definition of Boolean |28/06/2016 |BB |
| | |Algebra | | |
|14 | |Tutorial |01/07/2016 | |
|15 | |Basic theorems and properties of Boolean algebra |02/07/2016 |BB |
|16 | | Boolean functions |04/07/2016 |BB |
|17 | |canonical and standard forms |05/07/2016 | |
|18 | |Tutorial class on unit-1 |05/07/2016 | |
|19 |2 |Gate level minimization – The map method |11/07/2016 |BB |
|20 | |three-Variable ,Four-variable and Five-Variable maps. |12/07/2016 |BB |
|21 | |Assignment test on unit-2 |12/07/2016 | |
|22 | |Six-variable map |15/07/2016 |BB |
|23 | |Tutorial |16/07/2016 | |
|24 | |Product of sums simplification |18/07/2016 |BB |
|25 | |Sum of product simplification, Don’t-care conditions |19/07/2016 |BB |
|26 | |NAND and NOR implementation |19/07/2016 |BB |
|27 | |other Two-level implementations: AND–OR–INVERT Implementation, and |22/07/2016 |BB |
|28 | |OR-AND-INVERT Implementation. |23/07/2016 |BB |
|29 | |Tutorial class on unit-2 |23/07/2016 | |
| | | | | |
|30 |3 |Combinational Circuits, Analysis procedure Design procedure |26/07/2016 |BB |
|31 | |Combinational circuits for different code conversion(BCD to excess-3 |26/07/2016 |BB |
| | |code) | | |
|32 | |Multiplier |29/07/2016 |BB |
|33 | |Binary Adder- Subtractor(half, full & binary adder) |30/07/2016 |BB |
|34 | |Tutorial |01/08/2016 | |
|35 | |Decimal Adder(BCD Adder) |02/08/2016 |BB |
|36 | |Binary multiplier, Magnitude comparator |02/08/2016 |BB |
|37 | |Decoders |05/08/2016 |BB |
|38 | |Encoders |06/08/2016 |BB |
|39 | |Tutorial |16/08/2016 | |
|40 | |Multiplexers and De-Multiplexers |16/08/2016 |BB |
|41 | |Tutorial class on unit-3 |19/08/2016 | |
| | | | | |
|42 |4 |Sequential circuits: ; |22/08/2016 |BB |
|43 | |latches(storage elements):SR and D-Latches |23/08/2016 |BB |
|44 | |Flip-Flops: Edge Trigger D-flip flop |23/08/2016 |BB |
|45 | |SR,JK,D and T-Flip-Flops |26/08/2016 |BB |
|46 | |Tutorial |27/08/2016 | |
|47 | |Analysis of clocked sequential circuits |29/08/2016 |BB |
|48 | |Design of counter: Ripple counter : |30/08/2016 |BB |
|49 | |Binary ripple counter, BCD Ripple counter and |30/08/2016 |BB |
|50 | |Tutorial |02/09/2016 | |
|51 | |Synchronous circuits :binary counter and |03/09/2016 |BB |
|52 | |Up-Down binary counter |06/09/2016 |BB |
|53 | |Asynchronous sequential circuits |06/09/2016 |BB |
|54 | |Other counter : Ring and Johnson counters |09/09/2016 |BB |
|55 | |Registers: Register with parallel load, |10/09/2016 |BB |
|56 | |Shift registers: serial transfer and serial adder and |13/09/2016 |BB |
|57 | |Universal shift register |13/09/2016 |BB |
|58 | |Tutorial |16/09/2016 | |
|59 | |Reduction of state and follow table |17/09/2016 |BB |
|60 | |Role free conditions |19/09/2016 |BB |
| | | |20/09/2016 | |
|61 |5 |Introduction to memory systems. Random-Access Memory |23/09/2016 |BB |
|62 | |Types of memories : RAM and ROM. Types of ROMs |24/09/2016 | |
|63 | |Address and data bus |26/09/2016 |BB |
|64 | |Memory Decoding |27/09/2016 |BB |
|65 | |Programmable logic Array, and |30/09/2016 |BB |
|66 | |programmable Array logic |01/10/2016 |BB |
|67 | |Hierarchy of memory in terms of capacity and access time |04/10/2016 |BB |
Lecture Schedule with expected dates
II Year B.Tech. CSE-I Sem B-Section Faculty: Dr. S Udaya Kumar w.e.f: 13/06/2016
|SL. |Unit No |Topic to be covered in One lecture |Expected dates |Teaching aids used |
|No | | | |LCD/OHP/BB |
|1 |1 |Digital Systems, Binary Numbers |15/06/2016 |BB |
|2 | |Number base conversions, Octal |15/06/2016 |BB |
| | |and Hexadecimal Numbers and | | |
|3 | |Other base conversions |17/06/2016 | |
|4 | |Complements, Signed binary numbers |17/06/2016 |BB |
|5 | |Tutorial |18/06/2016 | |
|6 | |Floating point representations |22/06/2016 | |
|7 | |Binary codes |22/06/2016 | |
|8 | |Error detecting and correcting |24/06/2016 | |
|9 | |Binary Storage and Registers, Binary logic |24/06/2016 |BB |
|10 | |Conversion from gray code to other codes |25/06/2016 |BB |
|11 | |Tutorial class on unit-1 |29/06/2016 | |
|12 | |Digital Logic Gates(AND,NAND,OR,Ex-OR,Ex-NOR ect.,) |29/06/2016 | |
|13 | |Boolean Algebra and– Basic Definitions, Axiomatic definition of Boolean |01/07/2016 |BB |
| | |Algebra | | |
|14 | |Tutorial |01/07/2016 | |
|15 | |Basic theorems and properties of Boolean algebra |02/07/2016 |BB |
|16 | | Boolean functions |06/07/2016 |BB |
|17 | |canonical and standard forms |06/07/2016 | |
|18 | |Tutorial class on unit-1 |09/07/2016 | |
|19 |2 |Gate level minimization – The map method |13/07/2016 |BB |
|20 | |three-Variable ,Four-variable and Five-Variable maps. |13/07/2016 |BB |
|21 | |Assignment test on unit-2 |15/07/2016 | |
|22 | |Six-variable map |15/07/2016 |BB |
|23 | |Tutorial |16/07/2016 | |
|24 | |Product of sums simplification |20/07/2016 |BB |
|25 | |Sum of product simplification, Don’t-care conditions |20/07/2016 |BB |
|26 | |NAND and NOR implementation |22/07/2016 |BB |
|27 | |other Two-level implementations: AND–OR–INVERT Implementation, and |22/07/2016 |BB |
|28 | |OR-AND-INVERT Implementation. |23/07/2016 |BB |
|29 | |Tutorial class on unit-2 |27/07/2016 | |
| | | |27/07/2016 | |
|30 |3 |Combinational Circuits, Analysis procedure Design procedure |29/07/2016 |BB |
|31 | |Combinational circuits for different code conversion(BCD to excess-3 |29/07/2016 |BB |
| | |code) | | |
|32 | |Multiplier |30/07/2016 |BB |
|33 | |Binary Adder- Subtractor(half, full & binary adder) |03/08/2016 |BB |
|34 | |Tutorial |03/08/2016 | |
|35 | |Decimal Adder(BCD Adder) |05/08/2016 |BB |
|36 | |Binary multiplier, Magnitude comparator |05/08/2016 |BB |
|37 | |Decoders |06/08/2016 |BB |
|38 | |Encoders |10/08/2016 |BB |
|39 | |Tutorial |10/08/2016 | |
|40 | |Multiplexers and De-Multiplexers |12/08/2016 |BB |
|41 | |Tutorial class on unit-3 |12/08/2016 | |
| | | | | |
|42 |4 |Sequential circuits: ; |13/08/2016 |BB |
|43 | |latches(storage elements):SR and D-Latches |17/08/2016 |BB |
|44 | |Flip-Flops: Edge Trigger D-flip flop |17/08/2016 |BB |
|45 | |SR,JK,D and T-Flip-Flops |19/08/2016 |BB |
|46 | |Tutorial |19/08/2016 | |
|47 | |Analysis of clocked sequential circuits |20/08/2016 |BB |
|48 | |Design of counter: Ripple counter : |24/08/2016 |BB |
|49 | |Binary ripple counter, BCD Ripple counter and |26/08/2016 |BB |
|50 | |Tutorial |27/08/2016 | |
|51 | |Synchronous circuits :binary counter and |31/08/2016 |BB |
|52 | |Up-Down binary counter |02/09/2016 |BB |
|53 | |Asynchronous sequential circuits |02/09/2016 |BB |
|54 | |Other counter : Ring and Johnson counters |03/09/2016 |BB |
|55 | |Registers: Register with parallel load, |07/09/2016 |BB |
|56 | |Shift registers: serial transfer and serial adder and |09/09/2016 |BB |
|57 | |Universal shift register |10/09/2016 |BB |
|58 | |Tutorial |16/09/2016 | |
|59 | |Reduction of state and follow table |17/09/2016 |BB |
|60 | |Role free conditions |21/09/2016 |BB |
| | | | | |
|61 |5 |Introduction to memory systems. Random-Access Memory |23/09/2016 |BB |
|62 | |Types of memories : RAM and ROM. Types of ROMs |24/09/2016 | |
|63 | |Address and data bus |28/09/2016 |BB |
|64 | |Memory Decoding |28/09/2016 |BB |
|65 | |Programmable logic Array, and |30/10/2016 |BB |
|66 | |programmable Array logic |30/09/2016 |BB |
|67 | |Hierarchy of memory in terms of capacity and access time |01/09/2016 |BB |
Lecture Schedule with expected dates
Faculty: D.Venkateswarlu
II Year B.Tech. CSE-I Sem C-Section w.e.f: 13/06/2016
|SL. |Unit No |Topic to be covered in One lecture |Expected dates |Teaching aids used |
|No | | | |LCD/OHP/BB |
|1 |1 |Digital Systems, Binary Numbers |13.06.2016 |BB |
|2 | |Number base conversions, Octal |15.06.2016 |BB |
| | |and Hexadecimal Numbers and | | |
|3 | |Other base conversions |16.06.2016 | |
|4 | |Complements, Signed binary numbers |16.06.2016 |BB |
|5 | |Tutorial |18.06.2016 | |
|6 | |Floating point representations |20.06.2016 | |
|7 | |Binary codes |22.06.2016 | |
|8 | |Error detecting and correcting |23.06.2016 | |
|9 | |Binary Storage and Registers, Binary logic |23.06.2016 |BB |
|10 | |Conversion from gray code to other codes |25.06.2016 |BB |
|11 | |Tutorial class on unit-1 |27.06.2016 | |
|12 | |Digital Logic Gates(AND,NAND,OR,Ex-OR,Ex-NOR ect.,) |29.06.2016 | |
|13 | |Boolean Algebra and– Basic Definitions, Axiomatic definition of Boolean |30.06.2016 |BB |
| | |Algebra | | |
|14 | |Tutorial |30.06.2016 | |
|15 | |Basic theorems and properties of Boolean algebra |02.07.2016 |BB |
|16 | | Boolean functions |04.07.2016 |BB |
|17 | |canonical and standard forms |06.07.2016 | |
|18 | |Tutorial class on unit-1 |07.07.2016 | |
|19 |2 |Gate level minimization – The map method |07.07.2016 |BB |
|20 | |three-Variable ,Four-variable and Five-Variable maps. |09.07.2016 |BB |
|21 | |Assignment test on unit-2 |11.07.2016 | |
|22 | |Six-variable map |13.07.2016 |BB |
|23 | |Tutorial |14.07.2016 | |
|24 | |Product of sums simplification |14.07.2016 |BB |
|25 | |Sum of product simplification, Don’t-care conditions |16.07.2016 |BB |
|26 | |NAND and NOR implementation |18.07.2016 |BB |
|27 | |other Two-level implementations: AND–OR–INVERT Implementation, and |20.07.2016 |BB |
|28 | |OR-AND-INVERT Implementation. |21.07.2016 |BB |
|29 | |Tutorial class on unit-2 |21.07.2016 | |
| | | |25.07.2016 | |
|30 |3 |Combinational Circuits, Analysis procedure Design procedure |27.07.2016 |BB |
|31 | |Combinational circuits for different code conversion(BCD to excess-3 code) |27.07.2016 |BB |
|32 | |Multiplier |30.07.2016 |BB |
|33 | |Binary Adder- Subtractor(half, full & binary adder) |01.08.2016 |BB |
|34 | |Tutorial |03.08.2016 | |
|35 | |Decimal Adder(BCD Adder) |04.08.2016 |BB |
|36 | |Binary multiplier, Magnitude comparator |04.08.2016 |BB |
|37 | |Decoders |16.08.2016 |BB |
|38 | |Encoders |18.08.2016 |BB |
|39 | |Tutorial |20.08.2016 | |
|40 | |Multiplexers and De-Multiplexers |22.08.2016 |BB |
|41 | |Tutorial class on unit-3 |24.08.2016 | |
| | | |25.08.2016 | |
|42 |4 |Sequential circuits: ; |25.08.2016 |BB |
|43 | |latches(storage elements):SR and D-Latches |29.08.2016 |BB |
|44 | |Flip-Flops: Edge Trigger D-flip flop |31.08.2016 |BB |
|45 | |SR,JK,D and T-Flip-Flops |01.09.2016 |BB |
|46 | |Tutorial |01.09.2016 | |
|47 | |Analysis of clocked sequential circuits |03.09.2016 |BB |
|48 | |Design of counter: Ripple counter : |05.09.2016 |BB |
|49 | |Binary ripple counter, BCD Ripple counter and |06.09.2016 |BB |
|50 | |Tutorial |07.09.2016 | |
|51 | |Synchronous circuits :binary counter and |07.09.2016 |BB |
|52 | |Up-Down binary counter |12.09.2016 |BB |
|53 | |Asynchronous sequential circuits |14.09.2016 |BB |
|54 | |Other counter : Ring and Johnson counters |15.09.2016 |BB |
|55 | |Registers: Register with parallel load, |15.09.2016 |BB |
|56 | |Shift registers: serial transfer and serial adder and |17.09.2016 |BB |
|57 | |Universal shift register |19.09.2016 |BB |
|58 | |Tutorial |21.09.2016 | |
|59 | |Reduction of state and follow table |22.09.2016 |BB |
|60 | |Role free conditions |22.09.2016 |BB |
| | | |24.09.2016 | |
|61 |5 |Introduction to memory systems. Random-Access Memory |26.09.2016 |BB |
|62 | |Types of memories : RAM and ROM. Types of ROMs |28.09.2016 | |
|63 | |Address and data bus |01.10.2016 |BB |
|64 | |Memory Decoding |03.10.2016 |BB |
|65 | |Programmable logic Array, and |27.10.2016 |BB |
|66 | |programmable Array logic |27.10.2016 |BB |
|67 | |Hierarchy of memory in terms of capacity and access time |31.10.2016 |BB |
Lecture Schedule with expected dates
Faculty: D.Venkateswarlu
II Year B.Tech. CSE-I Sem D-Section w.e.f: 13/06/2016
|SL. |Unit No |Topic to be covered in One lecture |Expected dates |Teaching aids used |
|No | | | |LCD/OHP/BB |
|1 |1 |Digital Systems, Binary Numbers |13 .06.2016 |BB |
|2 | |Number base conversions, Octal |14.06.2016 |BB |
| | |and Hexadecimal Numbers and | | |
|3 | |Other base conversions |15.06.2016 | |
|4 | |Complements, Signed binary numbers |15.06.2016 |BB |
|5 | |Tutorial | | |
|6 | |Floating point representations |18.06.2016 | |
|7 | |Binary codes |20.06.2016 | |
|8 | |Error detecting and correcting |21.06.2016 | |
|9 | |Binary Storage and Registers, Binary logic |22.06.2016 |BB |
|10 | |Conversion from gray code to other codes |22.06.2016 |BB |
|11 | |Digital Logic Gates(AND,NAND,OR,Ex-OR,Ex-NOR ect.,) |25.06.2016 | |
|12 | |Boolean Algebra and– Basic Definitions, Axiomatic definition of Boolean |27.06.2016 | |
| | |Algebra | | |
|13 | |Tutorial |28.06.2016 | |
|14 | |Basic theorems and properties of Boolean algebra |29.06.2016 |BB |
|15 | | Boolean functions |29.06.2016 |BB |
|16 | |canonical and standard forms |02.07.2016 | |
|17 | |Tutorial |04.07.2016 | |
|18 |2 |Gate level minimization – The map method |05.07.2016 |BB |
|19 | |three-Variable ,Four-variable and Five-Variable maps. |06.07.2016 |BB |
|20 | |Six-variable map |06.07.2016 |BB |
|21 | |Product of sums simplification |11.07.2016 | |
|22 | |Tutorial |12.07.2016 |BB |
|23 | |Sum of product simplification, Don’t-care conditions |13.07.2016 |BB |
|24 | |NAND and NOR implementation |13.07.2016 |BB |
|25 | |other Two-level implementations: AND–OR–INVERT Implementation, and |16.07.2016 |BB |
|26 | |OR-AND-INVERT Implementation. |18.07.2016 |BB |
|27 |3 |Combinational Circuits, Analysis procedure Design procedure |19.07.2016 |BB |
|28 | |Combinational circuits for different code conversion(BCD to excess-3 code) |20.07.2016 |BB |
|29 | |Multiplier |20.07.2016 |BB |
|30 | |Tutorial |23.07.2016 |BB |
|31 | |Binary Adder- Subtractor(half, full & binary adder) |25.07.2016 | |
|32 | |Decimal Adder(BCD Adder) |26.07.2016 |BB |
|33 | |Binary multiplier, Magnitude comparator |27.07.2016 |BB |
|34 | |Decoders |27.07.2016 |BB |
|35 | |Tutorial |30.07.2016 | |
|36 | |Encoders |01.08.2016 |BB |
|37 | |Multiplexers and De-Multiplexers |02.08.2016 |BB |
|38 |4 |Sequential circuits: ; |03.08.2016 |BB |
|39 | |latches(storage elements):SR and D-Latches |03.08.2016 |BB |
|40 | |Tutorial |06.08.2016 | |
|41 | |Flip-Flops: Edge Trigger D-flip flop |16.08.2016 |BB |
|42 | |SR,JK,D and T-Flip-Flops |17.08.2016 |BB |
|43 | |Analysis of clocked sequential circuits |17.08.2016 | |
|44 | |Design of counter: Ripple counter : |20.08.2016 |BB |
|45 | |Tutorial |22.08.2016 | |
|46 | |Binary ripple counter, BCD Ripple counter and |23.08.2016 |BB |
|47 | |Synchronous circuits :binary counter and |24.08.2016 |BB |
|48 | |Up-Down binary counter |24.08.2016 |BB |
|49 | |Asynchronous sequential circuits |27.08.2016 |BB |
|50 | |Tutorial |29.08.2016 | |
|51 | |Other counter : Ring and Johnson counters |05.09.2016 |BB |
|52 | |Registers: Register with parallel load, |06.09.2016 |BB |
|53 | |Shift registers: serial transfer and serial adder and |07.09.2016 |BB |
|54 | |Universal shift register |12.09.2016 |BB |
|55 | |Tutorial |13.09.2016 | |
|56 | |Reduction of state and follow table |14.09.2016 |BB |
|57 | |Role free conditions |14.09.2016 |BB |
|58 | |Assignment test |17.09.2016 | |
|59 |5 |Introduction to memory systems. Random-Access Memory |19.09.2016 |BB |
|60 | |Types of memories : RAM and ROM. Types of ROMs |21.09.2016 | |
|61 | |Address and data bus |21.09.2016 |BB |
|62 | |Memory Decoding |26.09.2016 |BB |
|63 | |Programmable logic Array, and |27.09.2016 |BB |
|64 | |programmable Array logic |03.10.2016 |BB |
|65 | |Tutorial |31.10.2016 | |
|66 | |Hierarchy of memory in terms of capacity and access time |0.11.2016 |BB |
14. Detailed notes
Unit-I
BINARY SYSTEMS
Philosophy of Number Systems
Numbering System:
Many number systems are in use in digital technology. The most common are the decimal, binary, octal, and hexadecimal systems. The decimal system is clearly the most familiar to us because it is a tool that we use every day. Examining some of its characteristics will help us to better understand the other systems. In the next few pages we shall introduce four numerical representation systems that are used in the digital system. There are other systems, which we will look at briefly.
Decimal
Binary
Octal
Hexadecimal
Decimal System:
The decimal system is composed of 10 numerals or symbols. These 10 symbols are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. Using these symbols as digits of a number, we can express any quantity. The decimal system is also called the base-10 system because it has 10 digits.
|103 |102 |101 |100 | |10-1 |10-2 |10-3 |
|=1000 |=100 |=10 |=1 |. |=0.1 |=0.01 |=0.001 |
|Most Significant Digit | | | |Decimal point | | |Least Significant|
| | | | | | | |Digit |
Even though the decimal system has only 10 symbols, any number of any magnitude can be expressed by using our system of positional weighting.
|[pi|Decimal Examples |
|c] | |
3.1410
5210
102410
6400010
|[pic]|Binary System |
In the binary system, there are only two symbols or possible digit values, 0 and 1. This base-2 system can be used to represent any quantity that can be represented in decimal or other base system.
|23 |22 |21 |20 | |2-1 |2-2 |2-3 |
|=8 |=4 |=2 |=1 |. |=0.5 |=0.25 |=0.125 |
|Most Significant Digit | | | |Binary point | | |Least Significant|
| | | | | | | |Digit |
|[pi|Binary Counting |
|c] | |
The Binary counting sequence is shown in the table:
|23 |22 |21 |20 |Decimal |
|0 |0 |0 |0 |0 |
|0 |0 |0 |1 |1 |
|0 |0 |1 |0 |2 |
|0 |0 |1 |1 |3 |
|0 |1 |0 |0 |4 |
|0 |1 |0 |1 |5 |
|0 |1 |1 |0 |6 |
|0 |1 |1 |1 |7 |
|1 |0 |0 |0 |8 |
|1 |0 |0 |1 |9 |
|1 |0 |1 |0 |10 |
|1 |0 |1 |1 |11 |
|1 |1 |0 |0 |12 |
|1 |1 |0 |1 |13 |
|1 |1 |1 |0 |14 |
|1 |1 |1 |1 |15 |
In additional to binary and decimal, two other number systems find wide-spread applications in digital systems. The octal (base-8) and hexadecimal (base-16) number systems are both used for the same purpose- to provide an efficient means for representing large binary system.
|[pic]|Octal System |
The octal number system has a base of eight, meaning that it has eight possible digits: 0,1,2,3,4,5,6,7.
|83 |82 |81 |80 | |8-1 |8-2 |8-3 |
|=512 |=64 |=8 |=1 |. |=1/8 |=1/64 |=1/512 |
|Most Significant Digit | | | |Octal point | | |Least Significant|
| | | | | | | |Digit |
|[pi|Octal to Decimal Conversion |
|c] | |
2378 = 2 x (82) + 3 x (81) + 7 x (80) = 15910
24.68 = 2 x (81) + 4 x (80) + 6 x (8-1) = 20.7510
11.18 = 1 x (81) + 1 x (80) + 1 x (8-1) = 9.12510
12.38 = 1 x (81) + 2 x (80) + 3 x (8-1) = 10.37510
|[pic]|Hexadecimal System |
The hexadecimal system uses base 16. Thus, it has 16 possible digit symbols. It uses the digits 0 through 9 plus the letters A, B, C, D, E, and F as the 16 digit symbols.
|163 |162 |161 |160 | |16-1 |16-2 |16-3 |
|=4096 |=256 |=16 |=1 |. |=1/16 |=1/256 |=1/4096 |
|Most Significant Digit | | | |Hexa Decimal point | | |Least Significant|
| | | | | | | |Digit |
|[pi|Hexadecimal to Decimal Conversion |
|c] | |
24.616 = 2 x (161) + 4 x (160) + 6 x (16-1) = 36.37510
11.116 = 1 x (161) + 1 x (160) + 1 x (16-1) = 17.062510
12.316 = 1 x (161) + 2 x (160) + 3 x (16-1) = 18.187510
|[pi|Code Conversion |
|c] | |
Converting from one code form to another code form is called code conversion, like converting from binary to decimal or converting from hexadecimal to decimal.
|[pic]|Binary-To-Decimal Conversion |
Any binary number can be converted to its decimal equivalent simply by summing together the weights of the various positions in the binary number which contain a 1.
|Binary |Decimal |
|110112 | |
|24+23+01+21+20 |=16+8+0+2+1 |
|Result |2710 |
and
|Binary |Decimal |
|101101012 | |
|27+06+25+24+03+22+01+20 |=128+0+32+16+0+4+0+1 |
|Result |18110 |
You should have noticed that the method is to find the weights (i.e., powers of 2) for each bit position that contains a 1, and then to add them up.
|[pic]|Decimal-To-Binary Conversion |
There are 2 methods:
Reverse of Binary-To-Decimal Method
Repeat Division
|[pi|Reverse of Binary-To-Decimal Method |
|c] | |
|Decimal |Binary |
|4510 |=32 + 0 + 8 + 4 +0 + 1 |
| |=25+0+23+22+0+20 |
|Result |=1011012 |
|[pi|Repeat Division-Convert decimal to binary |
|c] | |
This method uses repeated division by 2.
Convert 2510 to binary
|Division |Remainder |Binary |
|25/2 |= 12+ remainder of 1 |1 (Least Significant Bit) |
|12/2 |= 6 + remainder of 0 |0 |
|6/2 |= 3 + remainder of 0 |0 |
|3/2 |= 1 + remainder of 1 |1 |
|1/2 |= 0 + remainder of 1 |1 (Most Significant Bit) |
|Result |2510 |= 110012 |
The Flow chart for repeated-division method is as follows:
[pic]
|[pic|Binary-To-Octal / Octal-To-Binary Conversion |
|] | |
|Octal Digit |0 |1 |2 |3 |4 |5 |6 |7 |
|Binary Equivalent |000 |001 |010 |011 |100 |101 |110 |111 |
Each Octal digit is represented by three binary digits.
Example:
100 111 0102 = (100) (111) (010)2 = 4 7 28
|[pi|Repeat Division-Convert decimal to octal |
|c] | |
This method uses repeated division by 8.
Example: Convert 17710 to octal and binary
|Division |Result |Binary |
|177/8 |= 22+ remainder of 1 |1 (Least Significant Bit) |
|22/ 8 |= 2 + remainder of 6 |6 |
|2 / 8 |= 0 + remainder of 2 |2 (Most Significant Bit) |
|Result |17710 |= 2618 |
|Binary | |= 0101100012 |
|[pic]|Hexadecimal to Decimal/Decimal to Hexadecimal Conversion |
Example:
2AF16 = 2 x (162) + 10 x (161) + 15 x (160) = 68710
|[pi|Repeat Division- Convert decimal to hexadecimal |
|c] | |
This method uses repeated division by 16.
Example: convert 37810 to hexadecimal and binary:
|Division |Result |Hexadecimal |
|378/16 |= 23+ remainder of 10 |A (Least Significant Bit)23 |
|23/16 |= 1 + remainder of 7 |7 |
|1/16 |= 0 + remainder of 1 |1 (Most Significant Bit) |
|Result |37810 |= 17A16 |
|Binary | |= 0001 0111 10102 |
|[pic|Binary-To-Hexadecimal /Hexadecimal-To-Binary Conversion |
|] | |
|Hexadecimal Digit |0 |1 |2 |3 |4 |5 |6 |7 |
|Binary Equivalent |0000 |0001 |0010 |0011 |0100 |0101 |0110 |0111 |
|Hexadecimal Digit |8 |9 |A |B |C |D |E |F |
|Binary Equivalent |1000 |1001 |1010 |1011 |1100 |1101 |1110 |1111 |
Each Hexadecimal digit is represented by four bits of binary digit.
Example:
1011 0010 11112 = (1011) (0010) (1111)2 = B 2 F16
|[pic|Octal-To-Hexadecimal Hexadecimal-To-Octal Conversion |
|] | |
Convert Octal (Hexadecimal) to Binary first.
Regroup the binary number by three bits per group starting from LSB if Octal is required.
Regroup the binary number by four bits per group starting from LSB if Hexadecimal is required.
Example:
Convert 5A816 to Octal.
|Hexadecimal |Binary/Octal |
|5A816 |= 0101 1010 1000 (Binary) |
| |= 010 110 101 000 (Binary) |
|Result |= 2 6 5 0 (Octal) |
Complement representation of negative numbers
Signed-Magnitude representation:
• This is the simplest method.
• Write the magnitude of the number in binary. Then add a 1 to the front of it if the number is negative and a 0 if it is positive.
• Examples: +7 would be 111 and then a 0 in front so 00000111 for an 8-bit representation.
-9 would be 1001 (+9) and then a 1 so 10001001 for an 8-bit representation.
• It is not the best method or representation because it makes computation awkward.
2’s complement representation:
• Most widely used method of representation.
• Positive numbers are represented as they are (simple binary).
• To get a negative number, write the positive number in binary, then change all 0’s to 1’s and 1’s to 0’s. Then add 1 to the number.
• Example : +7 would be 0111 in 4-bit 2’s complement.
To represent –5 we take +5 (0101) and then invert the digits (1010) and add 1
(1011). –5 is thus 1011.
• Suppose you already have a number that is in two’s complement representation and want to find its value in binary.
If the number starts with a 1 it is a negative number. If it starts with a 0 it is a positive number.
If it is a negative number, take the 2’s complement of that number. You will get the number in ordinary binary. The sign you already know. Let’s take 1101.
Take the 2’s complement and you get 0011. Since it started with a 1, it was
negative and the value is 0011 which is 3. The number represented by 1101 is –3
in 2’s complement.
Lets see how this system is better:
If we add +5 and -5 in decimal we get 0.
Let’s add them in 4-bit signed-magnitude. +5 is 0101 and –5 is 1101. On adding we get
10010. That is not zero.
Let’s do the same thing in 2’s complement. Adding 0101 (+5) and 1011 (-5) gives
10000. If we discard the carry of 1 we get 0000 – i.e. 0.
Thus addition works out ok for negative numbers in 2’s complement whereas it doesn’t in
sign magnitude.
Similarly, you can show that multiplication and subtraction all work in 2’s complement
but do not in other representations. The other number systems require much more
complicated hardware to implement basic mathematical functions. i.e.
add/subtract/multiply.
Sign-and-magnitude
|8 bit signed magnitude | |
|Binary |Signed |Unsigned |
|00000000 |+0 |0 |
|00000001 |1 |1 |
|... |... |... |
|01111111 |127 |127 |
|10000000 |−0 |128 |
|10000001 |−1 |129 |
|... |... |... |
|11111111 |−127 |255 |
One may first approach the problem of representing a number's sign by allocating one sign bit to represent the sign: set that bit (often the most significant bit) to 0 for a positive number, and set to 1 for a negative number. The remaining bits in the number indicate the magnitude (or absolute value). Hence in a byte with only 7 bits (apart from the sign bit), the magnitude can range from 0000000 (0) to 1111111 (127). Thus you can represent numbers from −12710 to +12710 once you add the sign bit (the eighth bit). A consequence of this representation is that there are two ways to represent zero, 00000000 (0) and 10000000 (−0). Decimal −43 encoded in an eight-bit byte this way is 10101011.
This approach is directly comparable to the common way of showing a sign (placing a "+" or "−" next to the number's magnitude). Some early binary computers (e.g. IBM 7090) used this representation, perhaps because of its natural relation to common usage. Sign-and-magnitude is the most common way of representing the significand in floating point values.
Ones' complement
|8 bit ones' complement | |
|Binary value |Ones' complement |Unsigned interpretation |
| |interpretation | |
|00000000 |+0 |0 |
|00000001 |1 |1 |
|... |... |... |
|01111101 |125 |125 |
|01111110 |126 |126 |
|01111111 |127 |127 |
|10000000 |−127 |128 |
|10000001 |−126 |129 |
|10000010 |−125 |130 |
|... |... |... |
|11111110 |−1 |254 |
|11111111 |−0 |255 |
Alternatively, a system known as ones' complement can be used to represent negative numbers. The ones' complement form of a negative binary number is the bitwise NOT applied to it — the complement of its positive counterpart. Like sign-and-magnitude representation, ones' complement has two representations of 0: 00000000 (+0) and 11111111 (−0).
As an example, the ones' complement form of 00101011 (43) becomes 11010100 (−43). The range of signed numbers using ones' complement is represented by −(2N−1−1) to (2N−1−1) and +/−0. A conventional eight-bit byte is −12710 to +12710 with zero being either 00000000 (+0) or 11111111 (−0).
To add two numbers represented in this system, one does a conventional binary addition, but it is then necessary to add any resulting carry back into the resulting sum. To see why this is necessary, consider the following example showing the case of the addition of −1 (11111110) to +2 (00000010).
'''binary decimal'''
11111110 -1
+ 00000010 +2
............ ...
1 00000000 0 s complement of N , i.e., its
diminished radix complement, is defined as (r n - 1) - N. For decimal numbers, r = 10
and r - 1 = 9, so the 9’s complement of N is (10n - 1) - N.
The 9>s complement of 546700 is 999999 - 546700 = 453299.
The 9>s complement of 012398 is 999999 - 012398 = 987601.
the 1’s complement of a binary number is formed by
changing 1’s to 0’s and 0’s to 1’s. The following are some numerical examples:
The 1’s complement of 1011000 is 0100111.
The 1’s complement of 0101101 is 1010010.
The (r - 1)>s complement of octal or hexadecimal numbers is obtained by subtracting
each digit from 7 or F (decimal 15), respectively.
Radix Complement
The r’s complement of an n‐digit number N in base r is defined as r n - N for N _ 0 and
as 0 for N = 0. Comparing with the (r - 1)>s complement, we note that the r’s complement
is obtained by adding 1 to the (r - 1)>s complement, since r n - N = [(r n - 1) - N] + 1.
the 10’s complement of 012398 is 987602
and
the 10’s complement of 246700 is 753300
The 10’s complement of the first number is obtained by subtracting 8 from 10 in the least
significant position and subtracting all other digits from 9. The 10’s complement of the
second number is obtained by leaving the two least significant 0’s unchanged, subtracting
7 from 10, and subtracting the other three digits from 9.
For example,
the 2’s complement of 1101100 is 0010100
and
the 2’s complement of 0110111 is 1001001
The 2’s complement of the first number is obtained by leaving the two least significant
0’s and the first 1 unchanged and then replacing 1’s with 0’s and 0’s with 1’s in the other
four most significant digits.
The 2’s complement of the complement restores the number to its original value .
The subtraction of two n‐digit unsigned numbers M - N in base r can be done as
follows:
1. Add the minuend M to the r’s complement of the subtrahend N. Mathematically,
M + (r n - N) = M - N + r n.
2. If M Ú N, the sum will produce an end carry r n, which can be discarded; what is
left is the result M - N.
3. If M 6 N, the sum does not produce an end carry and is equal to r n - (N - M),
which is the r’s complement of (N - M). To obtain the answer in a familiar form,
take the r’s complement of the sum and place a negative sign in front.
[pic]
PRIME IMPLICANTS:In choosing adjacent squares in a map, we must ensure that
(1) all the minterms of the function are covered when we combine the squares,
(2) the number of terms in the expression is minimized, and
(3) there are no redundant terms (i.e., minterms already covered by other terms).
.
. A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map. If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential.
for Example 3.6 , A_B_C_ _ B_CD_ _ A_BCD_ _ AB_C_ _ B_D_ _ B_C_ _ A_CD_
The prime implicants of a function can be obtained from the map by combining all
possible maximum numbers of squares. This means that a single 1 on a map represents
a prime implicant if it is not adjacent to any other 1’s.
Two adjacent 1’s form a prime implicant, provided that they are not within a group of four adjacent squares.
Four adjacent 1’s form a prime implicant if they are not within a group of eight adjacent
squares, and so on. The essential prime implicants are found by looking at each square
marked with a 1 and checking the number of prime implicants that cover it. The prime
implicant is essential if it is the only prime implicant that covers the minterm.
Consider the following four-variable Boolean function:
F(A, B, C, D) = _(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
[pic]
EXAMPLES:
Find all the prime implicants for the following Boolean functions, and determine which
are essential:
(a) * F (w, x, y, z) = _ (0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
(b) * F (A, B, C, D) = _ (0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
(c) F(A, B, C, D) = _(12, 3, 4, 5, 6, 7, 9, 11, 12, 13)
(d) F(w, x, y, z) = _(11, 3, 6, 7, 8, 9, 12, 13, 14, 15)
[pic]
[pic]
(UNIT-3)
MAPPING:
The map method presented here provides a simple, straightforward
procedure for minimizing Boolean functions. This method may be regarded as a pictorial
form of a truth table. The map method is also known as the Karnaugh map or K-map .
TWO VARIABLE MAP METHOD:
[pic]
[pic]
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[pic]
SIGNED NUMBERS:
[pic]
[pic]
[pic]
[pic][pic]
[pic]
HALF ADDERS AND FULL ADDERS:
The half adder design is carried out first, from
which we develop the full adder. Connecting n full adders in cascade produces a binary
adder for two n -bit numbers. The subtraction circuit is included in a complementing
circuit.
Half Adder: From the verbal explanation of a half adder, we find that this circuit needs two binary
inputs and two binary outputs. The input variables designate the augend and addend
bits; the output variables produce the sum and carry.
[pic]
Implementation of half-adder
The simplified expressions of sum and carry of a halfadder are:
[pic]
Full Adder
Addition of n-bit binary numbers requires the use of a full adder, and the process of addition proceeds on a bit-by-bit basis, right to left, beginning with the least significant bit. After the least significant bit, addition at each position adds not only the respective bits of the words, but must also consider a possible carry bit from addition at the previous position.
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs and two outputs. Two of the input variables, denoted by x and y , represent the two significant bits to be added. The third input, z , represents the carry from the previous lower significant position.
S = x_y_z + x_yz_ + xy_z_ + xyz
C = xy + xz + yz
The logic diagram for the full adder implemented in sum-of-products form is shown in fig .
[pic] [pic]
[pic]
[pic]
(UNIT-4)
FLIP FLOPS:
[pic]
[pic]
[pic]
[pic]
[pic]
(UNIT-4)
COUNTERS:
[pic][pic]
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[pic]
(UNIT-5)
PLA AND PAL:
The names PAL and PLA emerged from different vendors during the development of PLDs. The implementation of combinational circuits with PROM was demonstrated in this section. The design of combinational circuits with PLA and PAL is presented in these two sections.
The PLA is similar in concept to the PROM, except that the PLA does not provide full
decoding of the variables and does not generate all the minterms. The decoder is
replaced by an array of AND gates that can be programmed to generate any product
term of the input variables. The product terms are then connected to OR gates to provide
the sum of products for the required Boolean functions.
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The size of a PLA is specified by the number of inputs, the number of product terms,
and the number of outputs.
There are 2n * k connections between the inputs and the AND array,
k * m connections between the AND and OR arrays, and m connections associated with the XOR gates.
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The PAL is a programmable logic device with a fixed OR array and a programmable
AND array. Because only the AND gates are programmable, the PAL is easier to program
than, but is not as flexible as, the PLA
w(A, B, C, D) = g(2, 12, 13)
x(A, B, C, D) = g(7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = g(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = g(1, 2, 8, 12, 13)
Simplifying the four functions to a minimum number of terms results in the following
Boolean functions:
w = ABC_ + A_B_CD_
x = A + BCD
y = A_B + CD + B_D_
z = ABC_ + A_B_CD_ + AC_D_ + A_B_C_D
= w + AC_D_ + A_B_C_D
Note that the function for z has four product terms. The logical sum of two of these terms
is equal to w . By using w, it is possible to reduce the number of terms for z from four to
three.
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Each input has a buffer–inverter gate, and each output is generated by a fixed OR gate. There are four sections in the unit, each composed of an AND–OR array that is three wide, the term used to indicate that there are three programmable AND gates in each section and one fixed OR gate. Each AND gate has 10 programmable input connections.
21 Known gaps ,if any
1.counter Design with examples .
2 . practical exposer on logic gates
22. Discussion topics , if any
# Error Correction and error detected using HAMMING CODE
23. References, Journals, websites and E-links if any
Suggested Books
Text books
1 DIGITAL DESIGN – Third edition, M Morris Mano, Pearson Education/PHI.
Reference Text Books
1. Switching and Finite Automata Theory by Zvi. Kohavi, Tata McGraw Hill.
2. Switching and Logic Design, C.V.S. Rao, Pearson Education.
3. Digital Principles and Design – Donald D.Givone, Tata McGraw Hill, Edition.
4. Fundamentals of Digital Logic & Micro Computer Design , 5TH Edition, M. Rafiquzzaman John Wiley.
Subject Experts
Thomas L. Floyd
John P. Hayes
List of relevant Journals
1 Integration of an online digital logic design lab for it education
Conference ON Information Technology Education (formerly CITC ) archive
Proceedings of the 9th ACM SIGITE conference on Information Technology education
Digital And Analog Circuit Simulation with Ksimus
.../digital-and-analog-circuit-simulation-ksimus
24./Quality Measurement Sheets(to be enclosed after the semester)
Course End Survey
Teaching Evaluation
25. Student List
26. Group-Wise students list for discussion topics
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|Input |Output |Rule |
|(X.X)' |= X' |Idempotent |
|Decimal |8421 |2421 |5211 |Excess-3 |
|0 |0000 |0000 |0000 |0011 |
|1 |0001 |0001 |0001 |0100 |
|2 |0010 |0010 |0011 |0101 |
|3 |0011 |0011 |0101 |0110 |
|4 |0100 |0100 |0111 |0111 |
|5 |0101 |1011 |1000 |1000 |
|6 |0110 |1100 |1010 |1001 |
|7 |0111 |1101 |1100 |1010 |
|8 |1000 |1110 |1110 |1011 |
|9 |1001 |1111 |1111 |1100 |
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