Computer Science and Engineering 331
14:332:333
Project 2
Points: 30 Due: the week of 3/21-3/25
Read Appendix B.5 (on the CD) carefully. Design and simulate the VHDL for the 32-bit MIPS ALU with overflow and zero detect depicted in Figure B.5.12 (on the CD). The control lines and their functions are shown in Figures B.5.10, B.5.12 and Table B.5.13. Please note that the ALU structure on the CD is different from the ALU we had in class. Your VHDL description can be behavioral. You do not need to go to the gate level to build the ALU. For instance, if the ALUop is “0000”, you can calculate the result using the CSA “result ................
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