WordPress.com



B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- I

Subject: JAVA & J2EE Duration: 01 Hour

Sub Code: 10CS753 Max.Marks: 25

Semester: VII (A) Staff: Mr. Pavan Mahendrakar Date: 04/09/2016

Note: Answer any two full questions.

Q1.

a) Explain the following java buzzwords. i) Robust ii) Architectural neutral. 4

b) Explain different access controls( Specifiers) used in Java with appropriate examples 4.5

c) How arrays are defined in java. Explain with syntax and example. 4

Q2.

a) Define typecasting. Explain explicit type conversion with syntax and example 4

b) Explain the two uses of super with an example. 4.5

c) Write a java program to implement stack operations. 4

Q3.

a) What is constructor method & explain how it differs from other methods. 3

b) What is instance variable hiding? Illustrate how to overcome it with an example. 4.5

c) Distinguish between method overloading and method overriding in java with example. 5

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- I

Subject: JAVA & J2EE Duration: 01 Hour

Sub Code: 10CS753 Max.Marks: 25

Semester: VII (A) Staff: Mr. Pavan Mahendrakar Date: 04/09/2016

Note: Answer any two full questions.

Q1.

a) Explain the following java buzzwords. i) Robust ii) Architectural neutral. 4

b) Explain different access controls( Specifiers) used in Java with appropriate examples 4.5

c) How arrays are defined in java. Explain with syntax and example. 4

Q2.

a) Define typecasting. Explain explicit type conversion with syntax and example 4

b) Explain the two uses of super with an example. 4.5

c) Write a java program to implement stack operations. 4

Q3.

a) What is constructor method & explain how it differs from other methods. 3

b) What is instance variable hiding? Illustrate how to overcome it with an example. 4.5

c) Distinguish between method overloading and method overriding in java with example. 5

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- II

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: 15/04/2014

Note: Q1 is compulsory. Answer any 3 questions.

Q1.Write a note on any one bus arbitration scheme. 05

Q2. a) Explain internal organization of 16Mb DRAM chip, configured as 2Mx8 cells. 06

b) Define exception. Explain two kinds of exceptions. 04

Q3.a) In a situation where a number of devices capable of initializing interrupts are connected to the processor.

How should two or more simultaneous interrupts requests be handled? 05

b) Show the possible register configuration in DMA interface. Explain DMA. 05

Q4. a) Define the following i) Memory access time ii) memory cycle time iii) fast page mode. 05

b) Explain with an example rotate and shift instructions. 05

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- II

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: 15/04/2014

Note: Q1 is compulsory. Answer any 3 questions.

Q1.Write a note on any one bus arbitration scheme. 05

Q2. a) Explain internal organization of 16Mb DRAM chip, configured as 2Mx8 cells. 06

b) Define exception. Explain two kinds of exceptions. 04

Q3.a) In a situation where a number of devices capable of initializing interrupts are connected to the processor.

How should two or more simultaneous interrupts requests be handled? 05

b) Show the possible register configuration in DMA interface. Explain DMA. 05

Q4. a) Define the following i) Memory access time ii) memory cycle time iii) fast page mode. 05

b) Explain with an example rotate and shift instructions. 05

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- II

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mrs. Veena A. Patil Date: 15/04/2014

Note: Q1 is compulsory. Answer any 3 questions.

Q1.Write a note on any bus arbitration scheme. 05

Q2.a) Explain internal organization of 16Mb DRAM chip, configured as 2Mx8bit cells. 06

b) Define exception. Explain two kinds of exceptions. 04

Q3.a) In a situation where a number of devices capable of initializing interrupts are connected to the processor.

How two or more simultaneous interrupt requests should be handled? 05

b) With a block diagram explain the direct mapping between cache and main memory. 05

Q4.a) Show the organization of virtual memory address translation based in fixed length page.

Explain its working 05

b) Consider 3 ½ diameter disk with 20 recording surfaces and 15,000 tracks per surface. Each track

has 400 sectors and each sector contains 512bytes of data. Calculate latency and access time if

seek time is 6ms. 05

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- II

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mrs. Veena A. Patil Date: 15/04/2014

Note: Q1 is compulsory. Answer any 3 questions.

Q1.Write a note on any bus arbitration scheme. 05

Q2.a) Explain internal organization of 16Mb DRAM chip, configured as 2Mx8bit cells. 06

b) Define exception. Explain two kinds of exceptions. 04

Q3.a) In a situation where a number of devices capable of initializing interrupts are connected to the processor.

How two or more simultaneous interrupt requests should be handled? 05

b) With a block diagram explain the direct mapping between cache and main memory. 05

Q4.a) Show the organization of virtual memory address translation based in fixed length page.

Explain its working 05

b) Consider 3 ½ diameter disk with 20 recording surfaces and 15,000 tracks per surface. Each track

has 400 sectors and each sector contains 512bytes of data. Calculate latency and access time if

seek time is 6ms. 05

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- III

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: 11/05/2014

Note: Answer any 5 questions by selecting at least two from each part.

Part A

1. With a neat diagram explain direct and set associative mapping between cache and main memory.

2. With a neat diagram explain the translation of a virtual address to a physical address.

3. Define the following i) Hit Rate ii) Miss Penalty iii) Principal of Locality iv) Memory latency and Bandwidth.

4. Explain with neat diagram the memory hierarchy with respect to Speed, Size and Cost.

Part B

5. Explain briefly with neat diagram the single bus organization of the processor unit.

6. Write and explain the control sequences for the execution of following instruction ADD (R3), R1.

7. With a neat diagram explain the organization of micro programmed control unit.

8. With a block diagram explain complete processor.

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- III

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: 11/05/2014

Note: Answer any 5 questions by selecting at least two from each part.

Part A

1. With a neat diagram explain direct and set associative mapping between cache and main memory.

2. With a neat diagram explain the translation of a virtual address to a physical address.

3. Define the following i) Hit Rate ii) Miss Penalty iii) Principal of Locality iv) Memory latency and Bandwidth.

4. Explain with neat diagram the memory hierarchy with respect to Speed, Size and Cost.

Part B

5. Explain briefly with neat diagram the single bus organization of the processor unit.

6. Write and explain the control sequences for the execution of following instruction ADD (R3), R1.

7. With a neat diagram explain the organization of micro programmed control unit.

8. With a block diagram explain complete processor.

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

IA TEST- III

Subject: System Simulation & Modeling Duration: 01 Hour

Sub Code: 10CS82 Max.Marks: 25

Semester-VIII Staff: Mr. Prabhu Bevinamarad Date: 12/05/2013

Note: Answer any 5 questions by selecting at least two from each part.

Part A

1. Explain briefly the characteristics of a queuing system with neat diagram of single channel queue.

2. Explain briefly the steady state parameters of M/G/1 queuing model.

3. Explain Kendall’s notation for parallel server queueing system and interpret the meaning of following queueing models i) M/D/40/200/FCFS ii)M/G/1.

4. Explain any two long run measures of performance of queueing system.

5. Part B

6. Explain briefly with a neat diagram simulation in GPSS for single server queue model.

7. Explain three steps involved in model building, verification and validation with neat diagram.

8. Define calibration and explain the iterative process of calibrating a model.

9. Describe Naylor and finger three steps approach used for validation process.

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

IA TEST- III

Subject: System Simulation & Modeling Duration: 01 Hour

Sub Code: 10CS82 Max.Marks: 25

Semester-VIII Staff: Mr. Prabhu Bevinamarad Date: 12/05/2013

Note: Answer any 5 questions by selecting at least two from each part.

Part A

1. Explain briefly the characteristics of a queuing system with neat diagram of single channel queue.

2. Explain briefly the steady state parameters of M/G/1 queuing model.

3. Explain Kendall’s notation for parallel server queueing system and interpret the meaning of following queueing models i) M/D/40/200/FCFS ii)M/G/1.

4. Explain any two long run measures of performance of queueing system.

Part B

5. Explain briefly with a neat diagram simulation in GPSS for single server queue model.

6. Explain three steps involved in model building, verification and validation with neat diagram.

7. Define calibration and explain the iterative process of calibrating a model.

8. Describe Naylor and finger three steps approach used for validation process.

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- I

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: /03/2015

Note: Answer any 5 questions. Each Carries 05 marks.

1. Draw the connection b/w processor & memory and mention functions of each component in the connection.

2. Drive the basic performance equation. Discuss measures to improve the performance. 2.5+2.5M

3. What is arithmetic overflow? Add the following 5-bit signed numbers using 2’s complement and state whether overflow occurs. i. 8 and 14 ii.-10 and -5 2.5+2.5M

4. Explain with an example BIG-ENDIAN & LITTLE-ENDIAN method of byte addressing. 2.5+2.5M

5. What is addressing mode? Explain briefly with an example i) indirect mode ii) index mode. 1+2+2M

6. What is stack frame? Explain briefly with an example how stack frame is built and dismantled for a particular invocation of subroutine. 1+4M

7. Assume the register Ro contains the following binary pattern with carry flag=0. Demonstrate the following instruction. CF=

i). RotateL #2,Ro ii). RotateR #2,Ro iii). RotateLC #2,Ro iv). RotateRC #2,Ro 1+1+1.5+1.5M

8. Consider register R1 & R2 of a computer contains the decimal values 1400 & 1500. What is the effective address of the operand in each of the following instructions? Assume that the computer has 32-bit word length. 1.5+1.5+1.5+0.5M

I) LOAD 20(R1), R5 II) ADD (R1) +, R5 III) Store R5, 30(R1, R2) iv) Move #3000, R5

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- I

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: /03/2015

Note: Answer any 5 questions. Each Carries 05 marks.

1. Draw the connection b/w processor & memory and mention functions of each component in the connection.

2. Drive the basic performance equation. Discuss measures to improve the performance. 2.5+2.5M

3. What is arithmetic overflow? Add the following 5-bit signed numbers using 2’s complement and state whether overflow occurs. i. 8 and 14 ii.-10 and -5 2.5+2.5M

4. Explain with an example BIG-ENDIAN & LITTLE-ENDIAN method of byte addressing. 2.5+2.5M

5. What is addressing mode? Explain briefly with an example i) indirect mode ii) index mode. 1+2+2M

6. What is stack frame? Explain briefly with an example how stack frame is built and dismantled for a particular invocation of subroutine. 1+4M

7. Assume the register Ro contains the following binary pattern with carry flag=0. Demonstrate the following instruction. CF=

i). RotateL #2,Ro ii). RotateR #2,Ro iii). RotateLC #2,Ro iv). RotateRC #2,Ro 1+1+1.5+1.5M

8. Consider register R1 & R2 of a computer contains the decimal values 1400 & 1500. What is the effective address of the operand in each of the following instructions? Assume that the computer has 32-bit word length. 1.5+1.5+1.5+0.5M

I) LOAD 20(R1), R5 II) ADD (R1) +, R5 III) Store R5, 30(R1, R2) iv) Move #3000, R5

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- II

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: 13/04/2015

Note: Answer any 5 questions. Each Carries 05 marks.

1. Consider a situation where a number of devices capable of initializing interrupts are connected to the processor w.r.t. the above situation explain the following.

a) How can the processor obtain the starting address of the appropriate service routine? 2.5M

b) How should two or more simultaneous interrupts requests be handled? 2.5M

2. What is bus arbitration Logic? Explain briefly two approaches to bus arbitration. 1M+2M+2M

3. Define the following. 1M+1M+1M+1M+1M

i) Interrupt Service Routine ii) Interrupt Latency iii) Edge Triggering iv) Cycle Stealing v) Burst Mode.

4. Write a short note on Synchronous bus asynchronous buses. 2.5M+2.5M

5. With a neat diagram explain the organization of 1k*1 memory chip. D-1M+E-4M

6. Define the following. 1M+1M+1M+1M+1M

i) Memory access time ii) memory cycle time iii) fast page mode iv) Random Access memory v) Static Memories.

7. With a neat diagram explain internal organization of a 2M*8 dynamic memory chip. D-1.5+E-3.5

8. Differentiate between SRAM and DRAM. 2.5+2.5

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- II

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: 13/04/2015

Note: Answer any 5 questions. Each Carries 05 marks.

1. Consider a situation where a number of devices capable of initializing interrupts are connected to the processor w.r.t. the above situation explain the following.

c) How can the processor obtain the starting address of the appropriate service routine? 2.5M

d) How should two or more simultaneous interrupts requests be handled? 2.5M

2. What is bus arbitration Logic? Explain briefly two approaches to bus arbitration. 1M+2M+2M

3. Define the following. 1M+1M+1M+1M+1M

i) Interrupt Service Routine ii) Interrupt Latency iii) Edge Triggering iv) Cycle Stealing v) Burst Mode.

4. Write a short note on Synchronous bus asynchronous buses. 2.5M+2.5M

5. With a neat diagram explain the organization of 1k*1 memory chip. D-1M+E-4M

6. Define the following. 1M+1M+1M+1M+1M

i) Memory access time ii) memory cycle time iii) fast page mode iv) Random Access memory v) Static Memories.

7. With a neat diagram explain internal organization of a 2M*8 dynamic memory chip. D-1.5+E-3.5

8. Differentiate between SRAM and DRAM. 2.5+2.5

************************All the Best************************

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- III

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: 16/05/2015

Note: Answer any 5 questions by selecting at least two from each part.

1. With a neat diagram explain direct and set associative mapping between cache and main memory. 2.5M+2.5M

2. With a neat diagram explain the translation of a virtual address to a physical address. D-1.5M+ E-3.5M

3. Define the following i) Hit Rate ii) Miss Penalty iii) Principal of Locality iv) Memory latency and Bandwidth in burst mode. 1M+1M+1M+2M

4. Explain with neat diagram the memory hierarchy with respect to Speed, Size and Cost. D-1M+ E-4M

5. With neat diagram explain the single bus organization of the data path inside a processor. D-1.5M+ E-3.5M

6. Write and explain the control sequences for the execution of following instruction ADD (R3), R1. 4M+E-4M

7. With a neat diagram explain the organization of micro programmed control unit. D-1M+ E-4M

8. Define and discuss Amdahl’s law. 1M+ E-4M

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- III

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: 16/05/2015

Note: Answer any 5 questions by selecting at least two from each part.

1. With a neat diagram explain direct and set associative mapping between cache and main memory. 2.5M+2.5M

2. With a neat diagram explain the translation of a virtual address to a physical address. D-1.5M+ E-3.5M

3. Define the following i) Hit Rate ii) Miss Penalty iii) Principal of Locality iv) Memory latency and Bandwidth in burst mode. 1M+1M+1M+2M

4. Explain with neat diagram the memory hierarchy with respect to Speed, Size and Cost. D-1M+ E-4M

5. With neat diagram explain the single bus organization of the data path inside a processor. D-1.5M+ E-3.5M

6. Write and explain the control sequences for the execution of following instruction ADD (R3), R1. 4M+E-4M

7. With a neat diagram explain the organization of micro programmed control unit. D-1M+ E-4M

8. Define and discuss Amdahl’s law. 1M+ E-4M

B.L.D.E.A’s

V.P. Dr. P. G. H. College of Engineering & Technology, Bijapur.

Department of Computer Science and Engineering

Internal Assessment Test- III

Subject: computer organization Duration: 01 Hour

Sub Code: 10CS46 Max.Marks: 25

Semester-IV Staff: Mr. Prabhu Bevinamarad Date: 16/05/2015

Note: Answer any 5 questions by selecting at least two from each part.

1. With a neat diagram explain direct and set associative mapping between cache and main memory. 2.5M+2.5M

2. With a neat diagram explain the translation of a virtual address to a physical address. D-1.5M+ E-3.5M

3. Define the following i) Hit Rate ii) Miss Penalty iii) Principal of Locality iv) Memory latency and Bandwidth in burst mode. 1M+1M+1M+2M

4. Explain with neat diagram the memory hierarchy with respect to Speed, Size and Cost. D-1M+ E-4M

5. With neat diagram explain the single bus organization of the data path inside a processor. D-1.5M+ E-3.5M

6. Write and explain the control sequences for the execution of following instruction ADD (R3), R1. 4M+E-4M

7. With a neat diagram explain the organization of micro programmed control unit. D-1M+ E-4M

8. Define and discuss Amdahl’s law. 1M+ E-4M

-----------------------

|0 |

|0 |

................
................

In order to avoid copyright disputes, this page is only a partial summary.

Google Online Preview   Download