Memory

Memory

RWM

NVRWM

ROM

Random Access

SRAM DRAM

Non-Random Access

FIFO LIFO Shift Register CAM

EPROM E2PROM

FLASH

Mask-Programmed Programmable (PROM)

N Words Decoder

Memory Decoders

M bits

M bits

S0

Word 0

S1 S2

Word 1

A0

Word 2

Storage Cell

A1

S0 Word 0 Word 1 Word 2

Storage Cell

SN-2 Word N-2 SN_1 Word N-1

AK -1

Word N-2 Word N-1

Input-Output (M bits)

N words => N select signals Too many select signals

Input-Output (M bits)

Decoder reduces # of select signals K = log2N

1

Array-Structured Memory

Problem: ASPECT RATIO or HEIGHT >> WIDTH

AK AK+1

2L- K

Bit Line

Storage Cell Word Line

AL-1

Row Decoder

A0 AK -1

Sense Amplifiers / Drivers

M.2K

Amplify swing to rail-to-rail amplitude

Column Decoder

Selects appropriate word

Input-Output (M bits)

Array Decoding

2

Hierarchical Memory Arrays

Row Address

Column Address Block Address

Control Circuitry

Block Selector

Global Amplifier/Driver

I/O

Global Data Bus

Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

Memory Timing Definitions

Read Cycle

READ WRITE

Read Access

Read Access

Write Cycle

Data Valid

Write Access

DATA

Data Written

3

Memory Timing Approaches

MSB

LSB

Address

Bus

Row Address Column Address

RAS

Address Bus

CAS

Address

Address transition initiates memory operation

RAS-CAS timing

DRAM Timing Multiplexed Adressing

SRAM Timing Self-timed

Example: HM6264 8kx8 SRAM

4

HM6264 Interface Function Table

5

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