Implementation of an SDR in Verilog

Master of Science Thesis in Communication systems Department of Electrical Engineering, Link?ping University, 2016

Implementation of an SDR in Verilog

Anders Sk?rpe

Master of Science Thesis in Communication systems

Implementation of an SDR in Verilog

Anders Sk?rpe

LiTH-ISY-EX?16/5001?SE

Supervisor: Examiner:

Kent Palmkvist isy, Link?ping University

Daniel Nordgren Syntronic

H?kan Johansson isy, Link?ping University

Division of Communication systems Department of Electrical Engineering

Link?ping University SE-581 83 Link?ping, Sweden

Copyright ? 2016 Anders Sk?rpe

Abstract

This report presents an implementation of the software part in a software defined radio. The radio is not entirely implemented in software and therefore there are certain limitations on the received signal. The parts implemented are oscillator, decimation filter, carrier synchronization, time synchronization, package detection, and demodulation. Different algorithms were tested for the different parts to measure the power consumption. To understand how the number of bits used to represent the signal affects the power consumption, the number of bits was reduced from 20 bits to 10 bits. This reduction reduced the power consumption from 2.57mW to 1.89mW. A small change in the choice of algorithms was then made which reduced the power consumption to 1.86mW. Then the clock rate was reduced for some parts of the system which reduced the power consumption to 1.05mW.

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Acknowledgments

I would first like to express my gratitude to the people at Syntronic for giving me the opportunity to make this thesis possible. I would also like to thank my supervisors at ISY, H?kan Johansson and Kent Palmkvist, for discussing ideas and providing feedback. I would also like to thank Altera for providing a license for DSP Builder and Quartus Prime which was very helpful when implementing the system.

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