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`define PROG1SEL 3
`define PROG2SEL 2
`define PROG3SEL 1
`define PROG4SEL 0
/////////////////////////////////////////////////////////////////////////
//===============================================================
// PIC 16F84
// PIC - Designed by PP Troendle under Iain Mc Nally
//
//
//
//////////////////////////////////////////////////////////////////////////
`include "opcodes.v"
`timescale 100ps / 10 ps
module pic(PC, inext, Clock, init, porta, portb, M, To_File, IR);
// I/O declarations
output [12:0] PC; // address for external programm memory
output [7:0] To_File; // for LCD debug mode
output [7:0] M; // for LCD debug mode
input [13:0] inext; // next instruction
inout [7:0] porta, portb; // inout ports
input Clock, init; // system clock and reset
output [13:0] IR; // Instruction register
//wires
wire [12:0] PC; // the programm counter (from reg pcl,
pclath)
wire [13:0] inext; //next instruction
wire [7:0] porta, portb; //inout ports
wire Clock, init; //system clock and reset
wire [7:0] M, ALU_output; //ALU
wire [6:0] ALU_funct; //ALU
wire [7:0] Address_File; //FILE system
wire [7:0] To_File; //FILE system
wire [7:0] From_File; // FILE system
wire [7:0] Data_ram; //FILE system
wire WnR; //FILE system
wire Z; // ALU status bit
wire loadf, loadw; // control bits
wire loadliteral; // control bits
wire ram_en, opt_en, tmr_en, pcl_en, pch_en, sta_en, fsr_en;
wire tra_en, trb_en, poa_en, pob_en, ee1_en, ee2_en, eed_en, eea_en, int_en;
wire tra, trb;
//registers
reg [13:0] IR; // Instruction
register
reg [12:0] PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8; // PC stack
reg [7:0] pcl, pclath; // PC - the programm
counter register
reg [7:0] W; // the Accumulator
reg [7:0] tmr0, status, fsr, eedata, eeadr; // Registers
reg [7:0] intcon, option, eecon1, eecon2; // Registers
ram ram1(Clock, WnR , Address_File, To_File, Data_ram);
port port1(Clock, init, porta, From_File, To_File, loadf, tra_en, poa_en);
port port2(Clock, init, portb, From_File, To_File, loadf, trb_en, pob_en);
alu alu1(ALU_output, W, M, ALU_funct);
//ALU
assign Z = (ALU_output == 8'b00000000)? 1'b1:1'b0;
assign To_File = (IR[13:0]==`TRISA)||(IR[13:0]==`TRISB)? W : ALU_output;
///ALU SHOULD DO THAT
assign ALU_funct = IR[13:7];
assign M = ( loadliteral )? IR[7:0]: From_File;
//PC
assign PC = {pclath[4:0], pcl[7:0]};
//Control signals
assign WnR = ((ram_en)&&(loadf));
assign loadf = (
((IR[7]==1)&&(IR[13:12]==2'b00))|| //destination bit
is one , file
(IR[13:11]==3'b010)||tra||trb||
//`BCF,`BSF,`TRISA,`TRISB
((IR[13:8]==`CLRF)&&!(IR[7]==0)) ); //loadf not
required in case W dest (CLRW)
assign loadw = (
((IR[7]==0)&&(IR[11:8]!=4'b0000)&&
(IR[13:12]==2'b00))|| //destination bit is zero ,
W
(IR[13:12]==2'b11)|| //immediate
(IR[13:0]==`CLRW) ); //loadw required in case CLR
assign loadliteral = (IR[13:12]==2'b11); //immediate
//indirect addressing
assign Address_File[7:0] =(({status[5], IR[6:0]} == 'h00)||
({status[5], IR[6:0]} == 'h80))? fsr:({status[5],
IR[6:0]}); //RP0 value in status => 8 th bit
// FILE ENABLE
assign ram_en= (((Address_File >= 'h8C)&&(Address_File ................
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