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Verilog – System Design ExampleExample: Design a 4-bit by 4-bit Multiplier using Repetitive Add Algorithm.For example, if you wanted to multiply1010A0110B-------00111100ResultThe above can be accomplished by repeatedly adding 1010 six times (i.e., the B value).The datapath and the controller for this will appear as:19812057150052425605715001981205715011277601485903238500156210 A (4 bits) B(4 bits) Load A4945380156210 C O N T R O L L E R00 C O N T R O L L E R391668015621002430780342904 bit down Counter004 bit down Counter44196034290ClkA (4 bit Latch)00ClkA (4 bit Latch) Load Counter391668016256001981202540003215640254000113538017780838200147320685800139700822960139700Dec. Count175260055880175260055880260604055880 0288798063500 NOR 400 NOR 4441960266708-Bit Adder008-Bit Adder3246120177800123444013970000CountEq0325374017780 Ready4343400330200838201016000838201016004343400170180004419603810Result (8-bit FET Register)00Result (8-bit FET Register) Reset19812048260019812048260127254013208039776401701801272540154940 Done5364480109220050596801092200Load Result8382013208019812010160Clear Result 2080260000236982000020802600:Controller State Diagram: ______ Ready20116801524000Load A14173201054100Load Counter2324100104140Clear Result1417320190500 ________ Ready20497803810000 CountEq0 _______1577340457200157734045720Load Result = CountEq015773406096000236220064770 CountEq0208026068580001417320109220DoneCreate a new Altera project called MultiplierRepetitiveAdd by using the new project wizard. The different steps of the wizard are as shown below.Depending upon the complexity of the project, you can choose an appropriate device family.Select Verilog HDL when prompted for EDA Tool settings as shown below.Choose File->New and select the Verilog HDL option,Type the following code in the editor window.module OneBitAdder(a,b,cin,sum,cout); input a,b,cin; output sum,cout; assign sum = a ^ b ^ cin; assign cout = (a & b) | (a & cin) | (b & cin);endmodule Save the file in the MultiplierRepetitiveAdd folder with the name of OneBitAdder.v.Similarly add another file to the project with the following code and save it as EightBitAdder.v. module EightBitAdder(A, B, cin, Sum, cout);input[7:0] A,B;input cin;output[7:0] Sum;output cout;wire[7:0] ctemp;OneBitAdder add0(A[0],B[0],cin,Sum[0],ctemp[0]);OneBitAdder add1(A[1],B[1],ctemp[0],Sum[1],ctemp[1]);OneBitAdder add2(A[2],B[2],ctemp[1],Sum[2],ctemp[2]);OneBitAdder add3(A[3],B[3],ctemp[2],Sum[3],ctemp[3]);OneBitAdder add4(A[4],B[4],ctemp[3],Sum[4],ctemp[4]);OneBitAdder add5(A[5],B[5],ctemp[4],Sum[5],ctemp[5]);OneBitAdder add6(A[6],B[6],ctemp[5],Sum[6],ctemp[6]);OneBitAdder add7(A[7],B[7],ctemp[6],Sum[7],ctemp[7]);endmoduleAs you can see from the above code that the 8-bit adder uses 8 one-bit adder modules to form a ripple carry adder.Similarly create and save the following modules.module Reg4Latch(D,clk,Q); // save as Reg4Latch.vinput[3:0] D;input clk;output[3:0] Q;//reg[3:0] temp; // rather than declaring reg[3:0] temp, you can declar reg Q[3:0]reg[3:0]Q; // and assign D to Qalways @(clk,D) // latchbegin if (clk == 1'b1) Q = D;//temp = D;end//assign Q = temp;endmodulemodule Reg8FF(D,clk,clear,Q); // save as Reg8FF.vinput[7:0] D;input clk,clear;output[7:0] Q;reg[7:0] temp;always @(negedge clk) // Falling edge triggeredbegin if (clear == 1'b1) temp = 8'b00000000;else temp = D;endassign Q = temp;endmodulemodule NORG4(X,out); // save as NORG4.vinput[3:0] X;output out;assign out = ~(X[0]| X[1] | X[2] | X[3]);endmodulemodule DownCounter4(Data,clk,load,dec,Out); // save as DownCounter4.vinput[3:0] Data;input load, dec, clk;output[3:0] Out;reg[3:0] temp;always @(negedge clk)begin if (load == 1'b1) temp = Data; else begin if (dec == 1'b1)temp = temp - 1'b1; endendassign Out = temp;endmodulemodule Controller(ready,reset,counteq0,clk,loadA,loadCounter,decCount,clearResult,loadResult,done,state); // save as Controller.vinput ready,reset,counteq0,clk;output loadA,loadCounter,clearResult,decCount,loadResult,done;output[1:0] state;reg loadA,loadCounter,clearResult,loadResult,decCount,done; // same outputs can be declared as regreg[1:0] stateT;parameter s0=0, s1 = 1, s2 = 2;always @(negedge clk)begin if (reset == 1'b1) stateT = s0; else case(stateT)s0 : if (ready == 1'b0) stateT = s0;elsestateT = s1;s1 : if (counteq0 == 1'b0) stateT = s1;else stateT = s2;s2 : stateT = s0; endcaseendassign state = stateT;always @(stateT,clk,counteq0) // important parameters for sensitivity listbegin case(stateT)s0 : begin loadA = 1'b1; loadCounter = 1'b1;clearResult = 1'b1;loadResult = 1'b0;decCount = 1'b0;done = 1'b0; ends1 : begin loadA = 1'b0; loadCounter = 1'b0;clearResult = 1'b0;loadResult = ~counteq0 & clk; // without anding with clk, loadResult willdecCount = 1'b1; // will be high in multiple statesdone = 1'b0; ends2 : begin loadA = 1'b0; loadCounter = 1'b0;clearResult = 1'b0;loadResult = 1'b0;decCount = 1'b0;done = 1'b1; end endcaseendendmodulemodule DataPath(A, B, clk,ready,Prod,decCounter,loadCounter,loadA,clearResult,loadResult, counteq0,count); // save as DataPath.vinput[3:0] A,B;input clk,ready,decCounter,loadCounter,loadA,clearResult,loadResult;output[7:0] Prod;output counteq0;output[3:0] count;reg temp[7:0];wire[3:0] CounterOut;wire[7:0] AdderOut;wire[3:0] Aout;wire cout;wire[7:0] ResultOut;//-----------datapth components---------------Reg4Latch AReg(A,loadA,Aout);EightBitAdder add8({4'b0000,A},ResultOut,1'b0,AdderOut,cout);Reg8FF res8(AdderOut,loadResult,clearResult,ResultOut);DownCounter4 counter4(B,clk,loadCounter,decCounter,CounterOut);// parameters for Reg8FF: Data,clk,load,dec,OutNORG4 n4(CounterOut,counteq0);//--------------------------------------------assign Prod = ResultOut;assign count=CounterOut; // for debugging purposeendmodulemodule MultiplierRepetitiveAdd(A,B,ready,reset,clk,Result,done,state,count,loadResult);// save as MultiplierRepetitiveAdd.vinput[3:0] A,B; // state, count, loadResult outputs are for debugging purposeinput ready,reset,clk;output[7:0] Result;output[3:0] count;output loadResult;output done;wire[7:0] tempRes;output[1:0] state;wire[1:0] stateTemp;wire[3:0] countTemp;wire decCounter,loadCounter,loadA,clearResult,loadResultT,doneTemp,counteq0; DataPath dpath(A, B, clk,ready,tempRes,decCounter,loadCounter,loadA,clearResult,loadResultT, counteq0,countTemp); Controller control(ready,reset,counteq0,clk,loadA,loadCounter,decCounter,clearResult,loadResultT,doneTemp,stateTemp); assign Result = tempRes; assign done = doneTemp; assign state = stateTemp; assign count = countTemp; // for debugging purpose assign loadResult=loadResultT; // for debugging purposeendmoduleAdd another Verilog file for testbench to the project by choosing File->new. Type the following code in it.// testbench`timescale 1ns/100psmodule tbMultiplierRepetitiveAdd(); // save as tbMultiplierRepetitiveAdd.vreg[3:0] At,Bt;reg readyt,resett,clkt;wire[7:0] Result;wire done;wire[1:0] state; // inputs to module are declared as reg, outputs as wire in TBwire[3:0] count;wire loadResult;MultiplierRepetitiveAdd mrp(At,Bt,readyt,resett,clkt,Result,done,state,count,loadResult);initialbegin clkt = 1'b0; resett = 1'b1; #15 resett = 1'b0;endinitialbegin readyt = 1'b0; #30 readyt = 1'b1; #20 readyt = 1'b0;endinitialbegin At = 4'b1010; Bt = 4'b0110;endalwaysbegin #5 clkt = ~clkt;endinitial#200 $finish;endmoduleFrom the Assignments->Settings menu, click on the TestBenches… button as shown below.Then click on the New button:Then type the name of the testbench file i.e., tbMultiplierRepetitiveAdd.v as shown below.After selecting the testbench file, click on the Add button as shown above.Click on the OK button, then OK button in the next dialog.Then click on Apply and OK.Now the testbench will be compiled along with rest of the Verilog code for the project.From the Processing menu, choose “Start Compilation”. If there are no errors reported, you can simulate your project by choosing Tools->Run Simulation Tool ->RTL Simulation as shown below.This will launch the ModelSim and run the project to end of simulation time. When it prompts you to “Are you sure you want to finish?”, choose “NO”.Then right click in the waveform area and choose “Zoom full” as shown below.This will show the complete simulation for your design as shown below. ................
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