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Program: BE Electronics Engineering Curriculum Scheme: Revised 2016Examination: Third Year Semester V Course Code: ELXDLO5013 and Course Name: ASIC VerificationTime: 1 hour Max. Marks: 50============================================================================== Note to the students :- All the Questions are compulsory and carry equal marks . Q1. 2 data type of verilog wire and resister combined into one type in system verilogOption A:WireOption B:RegisterOption C:LogicOption D: Input outputQ2.Type of test benches Option A:Static and dynamicOption B:Static and flatOption C:Flat and layeredOption D:Static and layeredQ3.Which breaks down higher level commands into low level commandsOption A:AgentOption B:TestOption C:StimulusOption D:DUTQ4.Logic type has 4 states defined as Option A:0,1Option B:X,ZOption C:0,ZOption D:0,1,X,ZQ5.md [I] [ j] is an example of Option A:Single array Option B:Single dimensional arrayOption C:Column arrayOption D: Multidimensional arrayQ6.Simulation phase involves following stepsOption A:Build , taskOption B:Build, run , shareOption C:Build, run , wrap upOption D: Run, buildQ7. In System Verilog, if a programmer wants to call a function and ignore its return value programmer has to cast the result to ……Option A:VoidOption B:NullifyOption C:MainOption D: FloatQ8. If you have a System Verilog task that does not consume time, you should make it a …………. function, which is a function that does not return a value.Option A:VoidOption B:NullifyOption C:MainOption D: FloatQ9.Create a 512 location integer array Option A:int my_array[513:0];Option B:int my_array[511:0]; Option C:int my_array[512:0]; Option D: int my_array[510:0]; Q10. Create a 9-bit address variable to index into the array bitOption A:[8:0] const;Option B:[9:0] addr;Option C:[8:0] int;Option D: [8:0] addr;Q11. Call a task, my_task(), and pass it the array and the address Option A:my_task(addr, addr);Option B:my_task(locate, location);Option C:my_task(location, addr);Option D: my_task(location, location);Q12. Compilation Unit Scope is also referred asOption A:$unitOption B:$scopeOption C:$compileOption D:$exitQ13.…………. is the procedural code that manipulates variables, contained in tasks and functions? Option A:MethodOption B:PrototypeOption C:ObjectOption D: HandleQ14. fork...join_none can be used toOption A:Stop an execution Option B:Start a thread Option C:End a thread Option D: To sequentially run the statementsQ15.Wait fork is used to Option A:Waits for all child processes to endOption B:Waits for parent processes to endOption C:Wait for the parent process to execute Option D: Wait for child process to start an executionQ16. What is used to pass information in system Verilog? Option A:MailboxOption B:SemaphoresOption C:Synchronized threads Option D: TransactorsQ17.What is inter process communication?Option A:Communication within the processOption B:Communication between two process Option C:Communication between two threads of same processOption D:Communication within two threads of same processQ18.What is the keyword to create a semaphore?Option A:NewOption B:GetOption C:PutOption D: CreateQ19. What command is used to terminate threads?Option A:DisableOption B:TerminateOption C:EndOption D: finishQ20.Target to the compilation of Verification process is Option A:Functional Coverage 100% and code coverage is not consideredOption B:Functional Coverage 100% and code coverage is 100%Option C:Code coverage should be 100% and Functional Coverage is not considered.Option D:If all the test cases inQ21.In the given code snippet, statement 2 will executed atinitial begin#5 x= 1’b0;// statement 1# 15 y= 1b’1; //statement 2EndOption A:15Option B:20Option C:5Option D: Current Simulation TimeQ22. If A= 4b`001x and B= 4b`1011, then result of A+B will beOption A:110xOption B:1100Option C:xxxxOption D: zzzzQ23.What is wrong with the following module definition?module A (p1, p2, , p4);input p1, p2;output p4;...endmoduleOption A:the missing port must be declaredOption B:missing ports are not allowed in module definitionsOption C:there must be at least one in out portOption D: nothing is wrongQ24. A set of values or transitions associated with a coverage-point can be explicitly excluded from coverage by specifying them asOption A:Ignore binsOption B:Illegal binsOption C:Implicit binsOption D: Explicit binsQ25.The Keyword differentiates the immediate assertion from the concurrent assertion isOption A:AssertOption B:PropertyOption C:If elseOption D: If ................
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