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Course : VT-FV :: VLSI Training in Functional Verification(Superset of all other courses except AAE Training)Course Features :17 Weeks Course (Next Batch Starting Date :?13-Dec-2014)Weekend Course : 4 Hours on Saturday & 4 Hours on Sunday(2:00PM - 6:00PM on both days)Tools Used : Questasim (Mentor Graphics)Demo Class : Attend 1st Session of course as a Demo classCourse Fee & Duration :INR 16,000/- (11 Weeks Training, does not include OVM/UVM Training, recommended for B.E/M.E students)INR 25,000/- (17 Weeks Training, includes OVM & UVM Training, 1 Project based on UVM/OVM methodology)VLSI TRAINING COURSE CONTENT :VLSI Design FlowSoC Architecture ConceptsOn-Chip Bus Protocols (AXI4.0, OCP3.0)Peripheral Bus Protocols(USB3.0/PCIEx Gen3)Advanced Verilog for VerificationSystemVerilog for Advanced VerificationASIC Verification ConceptsASIC Verification Methodologies : OVM & UVMPERL AutomationPROJECTS : Module(IP) Level Verification ProjectsProject#1 : SystemVerilog Based Project based Complex IP (USB, Ethernet, MemCtrl, Bridge, etc)Project#2 :SV & OVM/UVM Based Project based on Complex IP (UART, KBD, Bridge, etc)System on Chip(SoC) Verification ConceptsMock Interviews & Group DiscussionsStudent assignments for weekday practiceDetailed Course Structure :VLSI Design FlowSoC Design FlowIP Design FlowASIC/FPGA FlowSoC Architecture ConceptsARM Processor ArchitectureL1/L2/L3/L4 InterconnectsOn-Chip Bus ProtocolsBridge ProtocolsControllers ModulesPeripheral bus ProtocolsL1/L2 Cache, On-chip memoryBoot sequence & Sub System BringupLow Power Design TechniquesOn-Chip Bus Protocols (AXI4.0, OCP3.0)Signal DescriptionsChannel HandshakeAddressing OptionsAtomic AccessesResponse SignallingOrdering ModelData busesUnaligned TransfersClock, ResetAXI4 Specific revision updatesPeripheral Bus Protocols(USB3.0/PCIEx Gen3)USB3.0 Architectural OverviewData Flow ModelPhysical LayerLink LayerProtocol LayerAdvanced Verilog for VerificationEvent Regions and Event SchedulingTasks and FunctionsRace ConditionsRandomizationFile I/O operationsTB ConstructsSelf Checking TestbenchesSystemVerilog for Advanced VerificationArraysData Types and Data DeclarationsClassesOperators and ExpressionsScheduling SemanticsProcedural Statements and control flowProcesses & ThreadsTasks and FunctionsRandom ConstraintsInter Process synchronization and communicationClocking blocks, Program Block, AssertionsCoverage, InterfaceSystem Tasks and System FunctionsCompiler DirectivesDPIASIC Verification ConceptsSoC VerificationModule Level VerificationConstrained Random VerificationCoverage Driven VerificationDirected VerificationAssertion Based VerificationASIC Verification Methodologies : OVM & UVMOVM/UVM TB ArchitectureStimulus ModelingCreating OVCs and EnvironmentOVM Simulation PhasesTLM OverviewConfiguring TB EnvironmentOVM Sequences and SequencersConnecting multiple OVCsCreating TB infrastructureAdvanced OVM/UVM ConceptsPERL AutomationData types and ObjectsRegular Expressions & SubroutinesRegression environment setupPERL in verification environment setupPROJECTS : Module(IP) Level Verification ProjectsProject#1 : SystemVerilog Based ProjectProject#2 :SystemVerilog & OVM/UVM Based ProjectProject designs : Complex module (USB/Ethernet/KBD/MemContrlr/Bridge protocols etc)Specification analysisVerification Plan creationFeature & Scenario Listing downTB architecture creationBuilding Top level verification environmentTB component coding and integrationSanity test case and environment bring upComplete test case codingBuilding regression test suiteFunctional coverage and code coverage analysisSystem on Chip(SoC) Verification ConceptsProject Category : Medium complex SoCTB Architecture creationBuilding top level verification environmentTB component coding and integrationSanity test case and environment bring upComplete test case codingFunctional, Timing, Power &Performance TestsReset Value, Register access, Interrupt, Power Related, Functional TestsBuilding regression test suiteMock Interviews & Group Discussions?(Session# 16 & 28)Mock Interviews covering all aspects of Functional VerificationGroup discussion on Project assigned to studentsAssignments provided to student during courseVIP Developmet for one of OCP/Wishbone/APB/Ethernet ProtocolsVerification of PCIEx Physical Layer LTSSM FSM from scrachFunctional Verifcation of UART/AXI-DMA/OCP2AXI Bridge from scratch ................
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