THE CENTRAL PROCESSING UNIT - GURUIGNOU

Indira Gandhi National Open University School of Computer and Information Sciences

MCS - 012 COMPUTER ORGANISATION & ASSEMBLY LANGUAGE PROGRAMMING

Thinking about Learning

Block

3

THE CENTRAL PROCESSING UNIT

UNIT 1

Instruction Set Architecture

5

UNIT 2

Registers, Micro-operations and Instruction Execution

31

UNIT 3

ALU Organisation

53

UNIT 4

The Control Unit

65

UNIT 5

Reduced Instruction Set Computer Architecture

83

Programme / Course Design Committee

Prof. Sanjeev K. Aggarwal, IIT, Kanpur Prof. M. Balakrishnan, IIT , Delhi Prof Harish Karnick, IIT, Kanpur Prof. C. Pandurangan, IIT, Madras Dr. Om Vikas, Sr. Director, MIT Prof. P. S. Grover, Sr. Consultant, SOCIS, IGNOU

Faculty of School of Computer and Information Sciences Shri Shashi Bhushan Shri Akshay Kumar Prof. Manohar Lal Shri V.V. Subrahmanyam Shri P.Venkata Suresh

Print Preparation Team

Block Writers: Mrs. Usha Dept. of Computer Sciences New Era Institute of IT & Professional Studies New Delhi

Mr. Akshay Kumar SOCIS, IGNOU

Prof. MPS Bhatia (Content Editor) (NSIT), New Delhi

Prof. A.K. Verma (Language Editor)

Course Coordinator: Shri Akshay Kumar

Block Production Team

Shri H.K Som, SOCIS

Acknowledgements To all the faculty members and Director of SOCIS, IGNOU for their comments on the course material.

August, 2004

?Indira Gandhi National Open University, 2004 ISBN ? 81 ? 266 ? 1384 - X

All rights reserved. No part of this work may be reproduced in any form, by mimeograph or any other means, without permission in writing from the Indira Gandhi National Open University. Further information on the Indira Gandhi National Open University courses may be obtained from the University's office at Maidan Garhi, New Delhi-110 068. Printed and published on behalf of the Indira Gandhi National Open University, New Delhi by The Director, SOCIS.

BLOCK INTRODUCTION

We have already discussed the von Neumann architecture and the basic components of the computer system along with an interconnection structure in the previous blocks of this course. In this block we will be discussing the CPU organization. However, as the main function of CPU is "to execute an instruction", the discussion about CPU must revolve around the term instruction. Hence we have started the discussion with the instruction set in the first unit. We have presented details about the characteristics, addressing schemes and formats of the instructions. In Unit 2, we have tried to break down the instruction execution cycle into several sub-cycles, which in turn consist of micro-operations. In addition to this we will discuss register organization in this unit. The third unit will focus on the functionality of the two main components of CPU, the ALU. The fourth unit discuss about the control unit, with the detailed discussion of the programmed control unit. Unit 5 covers RISC architecture.

FURTHER READINGS FOR THE BLOCK

1. William Stallings, Computer Organization and Architecture, Sixth Edition, PHI. 2. M. Morris Mano, Computer System Architecture, Third Edition, PHI. 3. D. Patterson and J. Hennessy, Computer Organization and Design: The

Hardware/ Software Interface. San Mateo, CA:Morgan Kaufmann. 4. A. Tanenbaum, Structured Computer Organization, PHI.

UNIT 1 INSTRUCTION SET ARCHITECTURE

Structure

1.0 Introduction 1.1 Objectives 1.2 Instruction Set Characteristics 1.3 Instruction Set Design Considerations

1.3.1 Operand Data Types 1.3.2 Types of Instructions 1.3.3 Number of Addresses in an Instruction 1.4 Addressing Schemes 1.4.1 Immediate Addressing 1.4.2 Direct Addressing 1.4.3 Indirect Addressing 1.4.4 Register Addressing 1.4.5 Register Indirect Addressing 1.4.6 Indexed Addressing Scheme 1.4.7 Base Register Addressing 1.4.8 Relative Addressing Scheme 1.4.9 Stack Addressing 1.5 Instruction Set and Format Design Issues 1.5.1 Instruction Length 1.5.2 Allocation of Bits Among Opcode and Operand 1.5.3 Variable Length of Instructions 1.6 Example of Instruction Format 1.7 Summary 1.8 Solutions/ Answers

Page No.

5 5 6 9

18

26

28 29 30

1.0 INTRODUCTION

The Instruction Set Architecture (ISA) is the part of the processor that is visible to the programmer or compiler designer. They are the parts of a processor design that need to be understood in order to write assembly language, such as the machine language instructions and registers. Parts of the architecture that are left to the implementation are not part of ISA. The ISA serves as the boundary between software and hardware.

The term instruction will be used in this unit more often. What is an instruction? What are its components? What are different types of instructions? What are the various addressing schemes and their importance? This unit is an attempt to answer these questions. In addition, the unit also discusses the design issues relating to instruction format. We have presented here the instruction set of MIPS (Microprocessor without Interlocked Pipeline Stages) processor (very briefly) as an example.

Other related microprocessors instruction set can be studied from further readings. We will also discuss about the complete instruction set of 8086 micro-processor in unit 1, Block 4 of this course.

1.1 OBJECTIVES

After going through this unit you should be able to:

? describe the characteristics of instruction set; ? discuss various elements of an instruction; ? differentiate various types of operands;

Instruction Set Architecture

5

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