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South Carolina State University

College of Industrial and Engineering Technology

University Center

Greenville, SC

A Limited Spectrum Receiver for Data Logging and Analysis of Radio Frequency Energy

Document Version 1.0

Submitted by:

Ronald Douglas Starwalt

Anderson, SC

Senior Project EET 460

Spring 2007

Dr. Mohammed Sarhan - Instructor/Adviser

Introduction

My proposed spectrum analyzer project was a construction project originally published in QST magazine in 1998. This project was to be different from the original in two aspects. The first difference was to be a reduced spectrum range covered by the analyzer. The purpose of the reduction in range is to exploit the availability of surplus digital interface components. The second difference was be a changed control and display interface. The original project required an oscilloscope to be used as a display. I proposed to modify the original analyzer and adapt it to a limited spectrum of 144 to 148 MHz and provide a digital interface for the input and output connections.

The construction and testing of my limited spectrum receiver/spectrum analyzer has provided many opportunities for innovation and discovery. Time constraints did not allow the completion of all I had planned for the project, but I was able to complete the core sections and have been able to demonstrate the fundamental operation as predicted and anticipated.

The digital control section of the project was abandoned although partially constructed. This section would have allowed some form of digital control of the control voltage for the 1st Local Oscillator section. As each section of the RF chain was constructed, it was tested and adjusted as needed to provide correct operation when all the sections were integrated into a working system. In the final result, a test adapter I built for evaluating performance was used to demonstrate the operation of the analyzer.

Table of Contents Page

1. Introduction 2

2. Problem Statements 4

3. List of Abbreviated Terms 5

4. System Description 6

5. Block Diagram of Limited Spectrum Receiver 7

6. Works Completed and Future Plans 8

7. Computer Simulations and Design 12

8. Results and Error Analysis 15

9. Literature Review and Internet Sources 19

List of Figures (includes Photos and Charts)

1. Figure 1 - Block Diagram of Limited Spectrum Receiver 7

2. Figure 2 - Photos of 300 MHz IDBPF 8

3. Figure 3 - Result of Network Analyzer test on 300 MHz IDBPF 8

4. Figure 4 - Photo of 1st LO and Mixer assembled 9

5. Figure 5 - Network analyzer result on 1st LO at 152 MHz 9

6. Figure 6 - Network analyzer result on 1st LO at 156 MHz 10

7. Figure 7 - Photo of 2nd LO PCB with POS-400 VCO installed 10

8. Figure 8 - Network analyzer result of 2nd LO and Mixer 11

9. Figure 9 - Result of online IDBPF design tool 12

10. Figure 10 - Analyzer result of 300 MHz IDBPF filter 13

11. Figure 11 - SPICE result of proposed DAC scaling circuit 14

12. Figure 12 - Voltage circuit for demonstrating SA operation 15

13. Figure 13 - Results of 8.4 VDC control on 1st LO 15

14. Figure 14 - Results of 8.5 VDC control on 1st LO 16

15. Figure 15 - Results of 8.6 VDC control on 1st LO 16

16. Figure 16 - Results of 8.7 VDC control on 1st LO 17

17. Figure 17 - Results of 8.8 VDC control on 1st LO 17

18. Figure 18 - Results of 8.9 VDC control on 1st LO 18

Problem Statements

As mentioned in the project proposal, mechanisms with circuitry that utilize radio frequency (RF) energy, present in all man-made and natural environments, may operate improperly when subjected to unwanted RF energy. This energy may, or may not, be in the same spectrum that is utilized in the operation of the product. This energy is referred to as interference and must be considered in the design of the mechanism or product. The original proposal for the project intended to provide the ability to repeatedly sweep a segment of the RF spectrum and detect the presence of RF energy above a minimum threshold or operate on single spectra for the purpose of monitoring. For this project, the RF spectrum from 144.00 to 148.00 MHz was studied.

The project was constructed to operate in a non-sweep mode. Frequency selection was to be accomplished with 12-bit digital inputs. The output is analog voltage, but the original proposal included a 12-bit digital section. At the end of the semester, the analog output can be applied to any meter or an external analog to digital converter (ADC) for observation and recording.

The targeted audience for the LSR construction is the college student or serious hobbyist. All components used through-hole circuit technology where available. Surplus items and components were used as well as the purchase of manufactured printed circuit boards for the core analyzer sections. Wes Hayward, W7ZOI, and Terry White, K7TAU designed the original spectrum analyzer this project is based on. Their project was published in QST magazine in August 1998.

List of Abbreviated Terms

AC - Alternating Current

ADC - Analog to Digital Converter

ARRL - American Radio Relay League

BPF - Band Pass Filter

CR - Communications Receiver

dB - Decibel

dBm - Decibel relative to a Milliwatt

DAC - Digital to Analog Converter

DC - Direct Current

FCC - Federal Communications Commission

IDBPF - Inter Digital Band Pass Filter

IF - Intermediate Frequency

ISM - Industrial, Scientific, Medical

LPF - Low Pass Filter

LSR - Limited Spectrum Receiver

LO - Local Oscillator

PCB - Printed Circuit Board

RF - Radio Frequency

SA - Spectrum Analyzer

mV - Millivolt - 1 x 10-3 Volt

mW - Milliwatt - 1 x 10-3 Watt

MHz - Megahertz - 1 x 106 Hertz

uW - Microwatt - 1 x 10-6 Watt

UHF - Ultra High Frequency

URL - Uniform Resource Locator

VCO - Voltage Controlled Oscillator

VHF - Very High Frequency

System Description

• Heterodyne circuitry is employed in the design

• A voltage-controlled oscillator (VCO) is used for mixer input

• The VCO could be controlled with a Digital-to-Analog Converter (DAC)

• The analog output is scaled for a panel meter or an analog-to-digital converter (ADC)

The limited spectrum receiver (LSR) has a superheterodyne receiver as the base component for receiving the desired input spectra. Superheterodyne receiver theory has been documented well in published literature and will be discussed only briefly in the appendix of this paper. The VCO used in the LSR has a wide range of adjustment and is spectrally pure for our purpose. The output of the LSR mixers, after filtration, will be amplified and scaled for measurement by an external digital meter.

A secondary goal for the LSR project, with necessary modification, could be possible application for solar radio astronomy. Radio spectra of interest to radio astronomy is protected by international agreements. This spectrum is usually different from communications and the Industrial-Scientific-Medicine (ISM) allocation, but with modifications the project could be used for such purposes.

Block Diagram of Limited Spectrum Receiver

Figure 1

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Works Completed and Future Plans

As presented, my project demonstrates the essentials of spectrum analysis. The single most time consuming section of the project was the 300 MHz inter-digital band-pass filter (IDBPF). Well over 60 hours went into the construction and adjustment of the filter.

Figure 2

Two Photos of the 300 MHz Inter-Digital Band-pass Filter (mounted on bottom of chassis cover removed to allow viewing of filter elements)

The IDBPF was tested and adjusted using a Hewlett Packard network analyzer. Below is the measured performance of the filter.

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Figure 3 Network Analyzer result of 300 MHz IDBPF tuning

The 1st LO and mixer module is shown in the following photo.

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Figure 4 1st LO and Mixer Assembly mounted in cast aluminum box

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Figure 5 Control Voltage result for 152 MHz 1SToperation

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Figure 6 Control Voltage result for 156 MHz 1st LO operation

The 2nd LO and mixer assembly introduced a feature of my project that differed markedly from the original design of Hayward and White. I removed the 100 MHz crystal based oscillator and replaced it with another VCO capable of producing a 290 MHz signal. The change to a VCO is not irreversible and the possibility exists that the original circuit could be installed and a switching scheme between the two oscillators employed. The following photo shows the VCO placement.

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Figure 7 Mini-Circuit POS-400 VCO on 2nd LO PCB

The empty pads on the right side of the photo are where the 100 MHz crystal-based oscillator would be installed in a normal build of the project.

The performance of this module was also tested. The following is the result of a control DC voltage and a 300 MHz driven IF into the module.

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Figure 8 2nd LO and Mixer Assembly test results

Marker 1 shows and indicated 10.376 MHz at a -14.77 dBm level. Marker 3 is the 300 MHz IF injected into the circuit. Marker 2 is the 290 MHz LO produced by the POS-400 VCO.

I would like to continue development of this project to include the proposed DAC/ADC sections. The DAC section was approximately 30 % complete and required the development of interface cabling to connect the micro-controller pcb to the circuit card containing the DAC. The micro-controller pcb assembly operates stand alone after programming via a PC development software system. Once completed, this would provide a sweeping operation capability to the project and allow additional testing regarding response time verses output voltage.

The final step would be the development of the ADC section to completely close the digital control loop and provide software analysis of signals.

Computer Simulation and Design

The 300 MHz IDBPF was simulated and designed with an online tool located at:



A 5 element filter was chosen for the best compromise of physical size and performance. The result of the online program is shown below.

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Figure 9 Result of Online IDBPF design tool

As mentioned previously, this filter required many hours of fabrication. Even after care was given to construction, the initial tests of the filter proved it was unusable! The lengths of the filter rods were reduced by approximately 2%. Tuning was successful afterward with the performance of the filter being very close to the designed ideal. The following photo shows another plot of the filter performance. Note the decibel values of the 299 and 301 MHz values and compare them to the design tool predictions.

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Figure 10 Analyzer result of 300 MHz IDBPF filter

The ideal loss of the filter at 300 MHz was 13.986 dB. The actual measure value for the filter at 300 MHz was 19.56 dB. I believe I can obtain better results with this filter, but the construction of the filter rods will have to be performed on a metal lathe. Eccentricities in my drilling method affected the performance. This phenomenon was evident during the tuning process and could be seen on the network analyzer display.

Additional software tools were used to design a scaling circuit for the proposed DAC section. The control voltage for the 1st LO needed to range from approximately 8.4 VDC to 8.9 VDC. If the 12-bit DAC had been used, the 0 - 10 VDC output would have to be scaled to fall within the range of the 1st LO operation. SPICE simulation was performed to provide a circuit that would have allowed this function.

Below is the circuit analysis result.

Figure 11 SPICE result of proposed DAC scaling circuit (not implemented in final design)

The SPICE simulation was an excellent test-bed and allowed quick analysis of the proposed circuitry. I have no doubt that if I employ the DAC in future plans for the project, it will operate as indicated.

Results and Error Analysis

I was able to test the operation of the integrated sections of the analyzer, even though the digital aspects of the project were not implemented. A test circuit was constructed that provided adjustment of the 1st LO control voltage. The 2nd LO control voltage was set, but was not adjusted during the collection of data.

Figure 12 - Voltage circuit for demonstrating SA operation

The results of the manual control voltage analysis were entered into an Excel workbook. Each control voltage was entered on a separate worksheet and a chart showing input frequency and output voltage was generated and inserted into the worksheet.

Figure 13 Results of 8.4 VDC control on 1st LO

Figure 14 Results of 8.5 VDC control on 1st LO

Figure 15 Results of 8.6 VDC control on 1st LO

Figure 16 Results of 8.7 VDC control voltage on 1st LO

Figure 17 Results of 8.8 VDC control voltage on 1st LO

Figure 18 Results of 8.9 VDC control voltage on 1st LO

I would like to draw the reader's attention to the X-axis of each of the preceding graphs. As the control voltage increments from 8.4 to 8.9, the initial value of the X-axis changes. This is in line with the desired response of the analyzer and indicates the IF of 300 MHz is indeed the result of a changed 1st LO and input frequency. If the 300 MHz IDBPF were too broad, the energy from unwanted products would spill over into the 2nd LO and mixer assembly. The resultant output would be a large output voltage over the entire range of control voltages and input frequencies.

Literature Review

ARRL Publications (American Radio Relay League)

The Handbook for Radio Amateurs 2001, 78th Edition, The American Radio Relay League, Inc., 2000

Chapter 26 of the 2001 Handbook for Radio Amateur (2001 Handbook) is titled "Test Procedures and Projects." A section of this chapter is dedicated to spectrum analyzers. It explains the theory and application of the device.

QST Official Journal of ARRL - published monthly

QEX A Forum for Communication Experimenters -published bimonthly

The ARRL is devoted to the promotion, education, and development of radio and electronics engineering. It is the amateur radio operator's lobby for Congress and a voice for his interests. Their publications were used extensively for research on this project.

Internet Sources

A few web sites exist (as of this writing) showing spectrum analyzer projects and support.

Yahoo Builders Group



Source for the QST Aug/Sep 1998 Analyzer parts



Inter Digital Band Pass Filter Design Tool



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