Generics--Motivation System Design w/ VHDL - Virginia Tech

System Design w/ VHDL

Generics and Configurations

pp. 104-107, 153-156, 261-264, 292-307,

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Generics--Motivation

z Oftentimes we want to be able to specify a property separately for each instance of a component

? Delay ? Bit width

z VHDL allows models to be parameterized with generics

ECE 4514

Martin 2003

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Generics--Motivation

z Allows one to make general models instead of making specific models for many different configurations of inputs, outputs, and timing information.

z Information passed into a design description from its environment.

ECE 4514

Martin 2003

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A Generic NAND Gate

entity NAND_GATE is generic (N: Natural := 2; D: Time := 10 ns); port (A: in Bit_Vector (1 to N); Z: out Bit);

end NAND_GATE;

ECE 4514

Martin 2003

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Algorithmic architecture for generic NAND gate

architecture NAND_N_D of NAND_GATE is begin NAND_CAL: process (A)

variable RESULT: Bit; begin

RESULT := '1'; for K in 1 to N loop

RESULT := RESULT and A(K); exit when RESULT = '0'; end loop; Z E, Z => T2);

G3: MY_NAND_GATE

generic map (D => 20 ns, N => 2)

port map (A(1) => T1, A(2) => T2, Z => Z_OUT);

ECE 4514

Martin 2003

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Notes on generic

z Generic information is static--it can't be changed during the simulation

? I.e. You can't have the simulation calculate the value that is going to be passed to the generic...

? Specified at compile time.

z Generic value is instance-specific

? Different instances of the same component can have different values.

ECE 4514

Martin 2003

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More generic examples

z An AND gate with parameterized rise/fall times:

ENTITY and2 IS GENERIC(rise, fall : TIME; load : INTEGER); PORT( a, b : IN BIT; c : OUT BIT);

END AND2;

ARCHITECTURE load_dependent OF and2 IS SIGNAL internal : BIT;

BEGIN internal A, I2=>B, S1=>SUM, C=>CARRY);

A

SUM

HA

B

CARRY

I1

S1

halfadd

I2

C

ECE 4514

Martin 2003

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Default Mapping Rules

z If the entity name is the same as the component name, then this entity is bound to the component

z If there are multiple architectures for the same entity (for example, DA_1, DA_2,...) the last compiled architecture for the entity is chosen

z Very dangerous to use defaults

ECE 4514

Martin 2003

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"Boiler Plate" Configuration

z Suppose you have a large system model, and you want to experiment with the configuration of a few subcomponents

z Procedure:

? Develop system model ? Create library for model ? Do not bind sub-components in model ? Use separate Configuration Declaration

ECE 4514

Martin 2003

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Example 1/3

z Example CPU:

entity CPU is port ( ....port declaration.... );

end CPU;

CPU ALU

architecture RISC of CPU is

component ALU

port (....port declaration.... );

NOTE:

end component;

Component

begin U1: ALU port map ( ....port declaration.... );

remains to be bound.

end RISC;

ECE 4514

Martin 2003

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Example 2/3

z More of the example:

entity ALU is port ( ....port declaration.... );

end ALU;

architecture SMALL of ALU is

begin

......insert body here....

end SMALL;

architecture FAST of ALU is

begin

......insert body here....

end FAST;

ECE 4514

Martin 2003

Perhaps several architectural

descriptions of the same entity.

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Example Configuration Declaration

configuration MYCONFIG of CPU is for RISC for U1 : ALU use entity work.ALU(FAST); end for; end for;

end MYCONFIG;

ECE 4514

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Configuration Declaration Syntax

My test configuration name configuration MYCONFIG of CPU is

Top-level entity which is being configured

for RISC for U1 : ALU

Name of architecture being configured

use entity work.ALU(FAST);

Note syntax

end for;

Configuration statement

end for;

end MYCONFIG;

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Martin 2003

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Common Errors

z Modifying the model of a component and forgetting to reanalyze the component prior to reuse

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Martin 2003

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Common Errors

z Generics can have their values defined in multiple places:

? within a model

? in a component instantiation (generic map)

? within an architecture in a component declaration

? within a configuration declaration

z Changing the value in one place may not have the intended effect due to precedence

ECE 4514

Martin 2003

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Common Errors

z When using default bindings of components, the name, type and mode of each signal in the component declaration must exactly match that of the entity

z This is dangerous.

ECE 4514

Martin 2003

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Common Errors

z Inheriting a generic value by way of default initializations in the component declaration may lead to unexpected values.

z This is dangerous.

ECE 4514

Martin 2003

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Summary

z Generics

? Parameterize a model

z Configurations

? Specify architectures and parameters

z Next time: Start synthesis

? Reading: pp. 381-392, 439-452.

ECE 4514

Martin 2003

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