EE 231 Fall 2010

EE 2010

Fall 2010

EE 231 ¨C Homework 6

Due October 8, 2010

1. Problem 4.16

Define the carry propagate and carry generate as

Pi = Ai + Bi

Gi = Ai Bi

respectively. Show that the output carry and the output sum of a full adder becomes

Ci+1 = (Ci0 G0i + P i0 )0

Si = (Pi G0i )Ci

Define Pi = Ai + Bi and Gi = Ai Bi . Show that Ci+1 = (Ci0 G0i + Pi0 )0 and Si = (Pi G0i ) ¨’ Ci

The output of a full adder is

Si

= Ai ¨’ Bi ¨’ Ci

Ci+1 = Ai Bi + Ai Ci + Bi Ci

Si = (Pi G0i ) ¨’ Ci

= [(Ai + Bi )(Ai Bi )0 ] ¨’ Ci

= [(Ai + Bi )(A0i + Bi0 )] ¨’ Ci

= [Ai A0i + Ai Bi0 + Bi A0i + Bi Bi0 ] ¨’ Ci

= [Ai Bi0 + A0i Bi ] ¨’ Ci

= Ai ¨’ Bi ¨’ Ci QED

Ci+1 = (Ci0 G0i + Pi0 )0

= (Ci0 G0i )0 Pi

= (Ci + Gi )Pi

= (Ci + Ai Bi )(Ai + Bi )

= Ci Ai + Ci Bi + Ai Bi Ai + Ai Bi Bi

= Ai Ci + Bi Ci + Ai Bi + Ai Bi

= Ai Ci + Bi Ci + Ai Bi QED

(C¡¯0 G¡¯

+ 0P¡¯) = 1C

0

C1

C¡¯ G¡¯

0 0

B0

A

G¡¯

0

P0 G¡¯0

P¡¯

0

0

C0

C¡¯

0

C0

1

(P0 G¡¯

) + 0C =0S

0

S0

EE 2010

Fall 2010

2. Using a decoder and external gates, design the combinational circuit defined by the following

three Boolean functions:

(a) F1 = x0 y 0 z + xz 0

F2 = x0 yz 0 + xy 0

F3 = xyz 0 + xy

Truth table:

x

0

0

0

0

1

1

1

1

y

0

0

1

1

0

0

1

1

z

0

1

0

1

0

1

0

1

F1

0

1

0

0

1

0

1

0

F2

0

0

1

0

1

1

0

0

F3

0

0

0

0

0

0

1

1

F1

x

2

y

2

z

20

0

1

2

3

4

5

6

7

2

1

F

2

F3

(b) F1 = (x + y 0 )z 0

F2 = xz + y 0 z + yz 0

F3 = (y + z 0 )x

Truth table:

x

0

0

0

0

1

1

1

1

y

0

0

1

1

0

0

1

1

z

0

1

0

1

0

1

0

1

F1

1

0

0

0

1

0

1

0

F2

0

1

1

0

0

1

1

1

F3

0

0

0

0

1

0

1

1

F1

x

22

y

21

z

20

0

1

2

3

4

5

6

7

F

2

F3

2

EE 2010

Fall 2010

3. Implement the following Boolean functions with a multiplexer:

(a) F (w, x, y, z) = ¦²(2, 3, 5, 6, 11, 14, 15)

w

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

x

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

y

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

z

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

F

0

0

1

1

0

1

1

0

0

0

0

1

0

0

1

1

F =0

F =1

F = z0

F =z

F =0

F = z0

F =0

F =1

0

1

2

3

4

5

6

7

z

0

0

1

F

S2 S1 S0

w

x

y

3

EE 2010

Fall 2010

(b) F (w, x, y, z) = ¦°(3, 10, 11)

w

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

x

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

y

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

z

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

F

1

1

1

0

1

1

1

1

1

1

0

0

1

1

1

1

F =1

F =z

F =1

F =1

F =1

F =0

F =1

F =1

0

1

2

3

4

5

6

7

z

1

1

1

0

1

1

F

S2 S1 S0

w

x

y

4. Write a Verilog dataflow description to implement the Boolean functions of Problem 3.

module hw6_p3(input w, x, y, z, output Fa, Fb);

// Fa = Sum (2,3,5,6,11,14,15)

// Fa = Prod (3,10,11)

// OR together minterms

assign Fa = (~w & ~x &

(~w & x &

( w & x &

of Fa

y & ~z) |

y & ~z) |

y & z);

// AND together maxterms of Fb

assign Fb = (~w | ~x | y | z) &

(~w & ~x &

( w & ~x &

y &

y &

( w | ~x |

y | ~z) &

endmodule

4

z) |

z) |

(~w &

( w &

x & ~y & z) |

x & y & ~z) |

( w | ~x |

y |

z);

EE 2010

Fall 2010

5. Implement a full adder with two 4x1 multiplexers. Note: the truth table for the full adder is:

x

0

0

0

0

1

1

1

1

y

0

0

1

1

0

0

1

1

Cin

0

1

0

1

0

1

0

1

0

Bin

0

1

Cout

0

0

0

1

0

0

1

1

0

1

2

3

Cout

0

1

2

3

Sum

S1 S0

x

y

5

Sum

0

1

1

0

1

0

0

1

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