Dual N-channel 450 V, 3.2 , 0.5 A SuperMESH3 Power MOSFET ...

Features

STS1DN45K3

Dual N-channel 450 V, 3.2 , 0.5 A SuperMESH3TM Power MOSFET in SO-8

Preliminary data

Type

VDSS

RDS(on) max

STS1DN45K3 450 V < 3.8

ID 0.5 A

Pw 1.7 W

100% avalanche tested Low input capacitances and gate charge Low gate input resistance

Application

Switching applications

Description

SuperMESH3TM is a new Power MOSFET technology that is obtained via improvements applied to STMicroelectronics' SuperMESHTM technology combined with a new optimized vertical structure. The resulting product has an extremely low on resistance, superior dynamic performance and high avalanche capability, making it especially suitable for the most demanding applications.

SO-8 Figure 1. Internal schematic diagram

Table 1. Device summary Order codes STS1DN45K3

Marking 1ll45

Packages SO-8

Packaging Tape and reel

April 2010

Doc ID 17338 Rev 1

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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Contents

Contents

STS1DN45K3

1

Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3

Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

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STS1DN45K3

1

Electrical ratings

Table 2. Symbol

Absolute maximum ratings Parameter

VDS VGS ID ID IDM (1)

PTOT

IAR

EAS dv/dt (2)

Drain-source voltage (VGS = 0) Gate-source voltage

Drain current (continuous) at TC = 25 ?C Drain current (continuous) at TC = 100 ?C Drain current (pulsed)

Total dissipation at TC = 25 ?C (dual operation) Total dissipation at TC = 25 ?C (single operation) Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25?C, ID = IAR, VDD = 50 V) Peak diode recovery voltage slope

Tstg Storage temperature Tj Max. operating junction temperature

1. Pulse width limited by safe operating area 2. ISD 0.5 A, di/dt TBD A/?s, VPeak < V(BR)DSS

Table 3. Symbol

Thermal data Parameter

Thermal resistance junction-amb max (single operation) Rthj-amb(1) Thermal resistance junction-amb max (dual operation)

1. When mounted on FR4 board (steady state)

Electrical ratings

Value 450 ? 30 0.5 0.32

2 1.7 1.3

0.5

TBD

TBD - 55 to 150

150

Unit V V A A A W W

A

mJ

V/ns ?C ?C

Value 62.5 78

Unit ?C/W ?C/W

Doc ID 17338 Rev 1

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Electrical characteristics

2

Electrical characteristics

STS1DN45K3

(TC = 25 ?C unless otherwise specified)

Table 4. Symbol

On /off states Parameter

Test conditions

V(BR)DSS

Drain-source breakdown voltage

ID = 1 mA, VGS = 0

IDSS

IGSS VGS(th) RDS(on)

Zero gate voltage

VDS = Max rating

drain current (VGS = 0) VDS = Max rating, TC=125 ?C

Gate-body leakage current (VDS = 0)

VGS = ? 20 V

Gate threshold voltage VDS = VGS, ID = 50 ?A

Static drain-source on resistance

VGS = 10 V, ID = 0.5 A

Min. Typ. Max. Unit

450

V

1 ?A 50 ?A

?10 ?A

3 3.75 4.5 V

3.2 3.8

Table 5. Symbol

Dynamic Parameter

Test conditions

Min. Typ. Max. Unit

Ciss Coss Crss

Input capacitance Output capacitance Reverse transfer capacitance

VDS =25 V, f = 1 MHz, VGS = 0

150

pF

-

30

- pF

6

pF

Co(tr)(1) Co(er)(2)

Equivalent capacitance time related

Equivalent capacitance energy related

VDS = 0 to 360 V, VGS = 0

-

TBD

-

pF

-

TBD

-

pF

RG

Intrinsic gate resistance

f = 1 MHz open drain

-

TBD

-

Qg

Total gate charge

VDD = 360 V, ID = 0.5 A,

Qgs Gate-source charge VGS = 10 V

Qgd Gate-drain charge

(see Figure 3)

6

nC

-

TBD

- nC

TBD

nC

1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS

2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS

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STS1DN45K3

Electrical characteristics

Table 6. Symbol

Switching times Parameter

td(on) tr

td(off) tf

Turn-on delay time Rise time Turn-off-delay time Fall time

Test conditions

VDD = 225 V, ID = 0.5 A, RG = 4.7 , VGS = 10 V (see Figure 4)

Min. Typ. Max Unit

TBD

ns

TBD

ns

-

-

TBD

ns

TBD

ns

Table 7. Symbol

Source drain diode Parameter

Test conditions

Min. Typ. Max. Unit

ISD Source-drain current ISDM (1) Source-drain current (pulsed)

-

VSD (2) Forward on voltage

ISD = 0.5 A, VGS = 0

-

trr Qrr IRRM

Reverse recovery time Reverse recovery charge Reverse recovery current

ISD = 0.5 A, di/dt = 100 A/?s VDD = 100 V (see Figure 7)

trr Qrr IRRM

Reverse recovery time Reverse recovery charge Reverse recovery current

ISD = 0.5 A, di/dt = 100 A/?s

VDD = 100 V, Tj = 150 ?C

-

(see Figure 7)

1. Pulse width limited by safe operating area

2. Pulsed: pulse duration = 300 ?s, duty cycle 1.5%

0.5 A 2A

1.6 V

TBD

ns

TBD

nC

TBD

A

TBD

ns

TBD

nC

TBD

A

Table 8. Symbol

Gate-source Zener diode Parameter

Test conditions

BVGSO

Gate-source breakdown voltage

Igs=? 1 mA (open drain)

Min. Typ. Max. Unit

30

V

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components

Doc ID 17338 Rev 1

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