The SpecC Methodology - University of California, Irvine

SpecC Methodology Tutorial

The SpecC Methodology

Andreas Gerstlauer

Center for Embedded Computer Systems University of California, Irvine



Outline

? System design ? SpecC design methodology ? Specification model ? Architecture model ? Communication model ? Implementation model ? Summary & Conclusions

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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SpecC Methodology Tutorial

System-On-Chip Design

?Processor Memory

IP Comp.

Interface

Interface

Processors IPs

Memories Busses

Specification + constraints

Interface

Bus Interface

Memory

Custom HW

System architecture + estimates

Registers ALUs/FUs Memories

Gates

Control Datapath

ROM

PC IR

RAM RF FUs

FSM State

IP Netlist Reg

Control Datapath

State

Mem RF

FSM State

Memory

ALU

RTL Implementation + results

? Specification to architecture to implementation ? Behavior to structure

1. System level: system specification to system architecture 2. RT level: component behavior to component microarchitecture

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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SpecC Methodology

Abstraction / Time Impl. detail / Simul. detail

functional

untimed / causality

structural timed

bus functional

timed

RTL/IS gates

cycleaccurate

gate delays

Synthesis flow

Capture

Specification model

Architecture exploration Architecture model

Communication synthesis

Communication model

Algor. IP

Comp. IP

Proto. IP

Validation flow

Compilation Validation Analysis Estimation

Compilation Validation Analysis Estimation

Compilation Validation Analysis Estimation

Hardware Interface Software

RTL IP

synthesis synthesis design

RTOS IP

Backend

Implementation model

Compilation

Validation Analysis Estimation

Simulation model Simulation model Simulation model Simulation model

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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SpecC Methodology Tutorial

Specification Model

? High-level, abstract model ? Pure system functionality ? Algorithmic behavior ? No implementation details

? No implicit structure / architecture ? Behavioral hierarchy

? Untimed ? Executes in zero (logical) time ? Causal ordering ? Events only for synchronization

Specification model Architecture exploration

Architecture model Communication synthesis

Communication model Backend

Implementation model

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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Specification Model Example

BB11

v1

B2

v2

B3

e2

Design hierarchy:

behavior Design() { int v1; B1 b1 ( v1 ); B2B3 b2b3( v1 );

void main(void) { b1.main(); b2b3.main();

} };

behavior B2B3( in int v1 ) { int v2; event e2; B2 b2( v1, v2, e2 ); B3 b2( v1, v2, e2 );

void main(void) { par { b2.main(); b3.main(); }

}};

Leaf behaviors:

behavior B1( out int v1) { void main(void) { ... v1 = ...

};

behavior B2( in int v1, out int v2, out event e2) {

void main(void) { ... v2 = f2( v1, ... ); notify( v2 ); ...

} };

behavior B3( in int v1, in int v2, in event e2) {

void main(void) { ... wait( e2 ); f3( v1, v2, ...); ...

} };

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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SpecC Methodology Tutorial

Specification Model Example (2)

? Message-passing communication ? Abstract communication ? Encapsulate communication

B2

B3

C2

Blocking, unbuffered message-passing channel:

interface Isend { void send( void *d, int size );

}; interface Irecv {

void recv( void *d, int size ); };

channel ChMP() implements ISend, IRecv { void send( void *d, int size ) { ... } void recv( void *d, int size ) { ... }

};

behavior B2( in int v1, ISend c2) {

void main(void) { ... v2 = f2( v1, ... ); c2.send( &v2, sizeof(v2) ); ...

} };

behavior B3( in int v1, IRecv c2) {

void main(void) { ... c2.recv( &v2, sizeof(v2) ); f3( v1, v2, ...); ...

} };

behavior B2B3( in int v1 ) { ChMP c2(); B2 b2( v1, c2 ); B3 b3( v1, c2 ); void main(void) { par { b2.main(); b3.main(); }

}};

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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Architecture Exploration

? Component allocation / selection ? Behavior partitioning ? Variable partitioning ? Scheduling

Specification model Architecture exploration

Architecture model Communication synthesis

Communication model Backend

Implementation model

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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SpecC Methodology Tutorial

Allocation, Behavior Partitioning

PE1 B2

BB11

v1

PE2

B3 C2

? Allocate PEs ? Partition behaviors ? Globalize communication

? Additional level of hierarchy to model PE structure

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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Model after Behavior Partitioning

BB11

PE1

PE2

v1

B13snd

CB13

B13rcv

B2

B3

C2

B34rcv

CB34

B34snd

Synchronization behaviors:

behavior BSnd( ISend ch ) { void main(void) { ch.send( 0, 0 );

}};

behavior BRcv( IRecv ch ) { void main(void) { ch.recv( 0, 0 );

}};

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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