EE382N: Embedded System Design and Modeling

EE382N: Embedded Sys Dsgn/Modeling

Lecture 8

EE382N: Embedded System Design and Modeling

Lecture 8 ? Computation Modeling & Refinement

Andreas Gerstlauer

Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu

Lecture 8: Outline

? Processor layers ? Application ? Task/OS ? Firmware ? Hardware

? Processor synthesis ? Software synthesis ? Hardware synthesis

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Lecture 8

General Processor Micro-Architecture

? Basic computation component is a processor (PE) ? Programmable, general-purpose software processor (CPU) ? Programmable special-purpose processor (e.g. DSPs) ? Application-specific instruction set processor (ASIP) ? Custom hardware processor

PE

Bus interface

CLK

Controller

Status lines

Datapath

t

Control signals

Functionality and timing (and power and ...)

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Computation Modeling (1)

? Structural RTL models

CPU

Controller

PC Fetch

IR

Decode

Load/store unit

CLK

Memory (data & progr.)

Datapath

Register file

ALU

HW

Controller

Next state logic

State

Output logic

Bus interface

CLK

Datapath

Register file

Memory

FU1

Software processor Sub-cycle accurate

Hardware processor

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Lecture 8

Computation Modeling (2)

? Behavioral RTL models (FSMD) ? Instruction-set simulation (ISS) models

? Purely functional (binary translation) [QEMU,...] ? Micro-architectural (RTL in C) [GEM5,...]

Binary

App. RTOS HAL

CPU

HW

ISS

CPU_CLK

Instruction set simulation (ISS) Cycle or timing accurate

HW_CLK

FSMD

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Computation Modeling (3)

? Host-compiled models ? Source-level application model

? Compile & execute natively ? Fast functional simulation

? Back-annotate timing and other metrics

? Abstract OS and processor models

? Transaction-level model (TLM) backplane

? C-based discrete-event simulation kernel [SpecC,SystemC]

Fast and accurate full-system simulation

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Lecture 8

Host-Compiled Computation Layers

CPU

Process B1() {

... waitfor(15000); ... waitfor(25000); ... };

P1 P2

OS HAL Drv ISR

Bus

Interrupts

? Application ? Process execution (C code) ? Execution timing

? OS & processor ? Operating system

? Real-time multi-tasking (RTOS model) ? Bus drivers (C code)

? Hardware abstraction layer (HAL)

? Interrupt handlers ? Media accesses

? Processor hardware

? Bus interfaces (I/O state machines) ? Interrupt suspension and timing

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Application Layer

? High-level, abstract programming model

? Hierarchical process graph

...

? ANSI C leaf processes ? Parallel-serial composition

CPU B1

... ...

? Abstract, typed inter-process

communication

B2

C1

B3

? Channels

C2

? Shared variables

Timed simulation of application functionality

? Annotate timing, energy, ...

? Granularity?

? Compiler optimizations?

? Dynamic architecture effects?

...

Logical time

0 5 10

Source profiling [SCE] Back-annotate from ISS

void f() { waitfor(5); ...

Predict from host activity

}

...

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Lecture 8

Source-Level Back-Annotation

? Retargetable backannotation flow ? Intermediate representation (IR)

a=b=c=0; if(a ................
................

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