The SpecC Methodology - University of California, Irvine

SpecC Methodology Tutorial

The SpecC Methodology

Andreas Gerstlauer

Center for Embedded Computer Systems

University of California, Irvine



Outline

?

?

?

?

?

?

?

System design

SpecC design methodology

Specification model

Architecture model

Communication model

Implementation model

Summary & Conclusions

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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SpecC Methodology Tutorial

System-On-Chip Design

?Processor

Control

IP

Comp.

Memory

Interface

PC

IR

Interface

Interface

Processors

IPs

Memories

Busses

Interface

Memory

Registers

ALUs/FUs

Memories

Gates

RF

Reg

Datapath

Mem

State

IP Netlist

State

FUs

Control

Bus

FSM

Datapath

RAM

ROM

FSM

RF

Memory

State

ALU

Custom HW

Specification

+ constraints

System architecture

+ estimates

RTL Implementation

+ results

? Specification to architecture to implementation

? Behavior to structure

1. System level: system specification to system architecture

2. RT level: component behavior to component microarchitecture

Copyright ?2001 A. Gerstlauer

The SpecC Methodology

3

SpecC Methodology

Abstraction / Time

Impl. detail / Simul. detail

Synthesis flow

Validation flow

Capture

functional

Algor.

IP

Compilation

untimed /

causality

Specification model

Architecture exploration

Comp.

IP

Compilation

structural

Architecture model

timed

Communication synthesis

bus

functional

Proto.

IP

Communication model

RTL

IP

Hardware Interface Software

synthesis synthesis design

gates

cycleaccurate

gate

delays

The SpecC Methodology

Implementation model

Backend

Simulation model

Validation

Analysis

Estimation

RTOS

IP

Compilation

RTL/IS

Simulation model

Validation

Analysis

Estimation

Compilation

timed

Simulation model

Validation

Analysis

Estimation

Simulation model

Validation

Analysis

Estimation

Copyright ?2001 A. Gerstlauer

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SpecC Methodology Tutorial

Specification Model

? High-level, abstract model

? Pure system functionality

? Algorithmic behavior

? No implementation details

Specification model

Architecture exploration

Architecture model

? No implicit structure / architecture

? Behavioral hierarchy

? Untimed

? Executes in zero (logical) time

? Causal ordering

? Events only for synchronization

Communication synthesis

Communication model

Backend

Implementation model

Copyright ?2001 A. Gerstlauer

The SpecC Methodology

5

Specification Model Example

Leaf behaviors:

B1

B1

behavior B1( out int v1) {

void main(void) {

��

v1 = ��

};

v1

B2

v2

behavior B2( in int

v1,

out int

v2,

out event e2) {

void main(void) {

��

v2 = f2( v1, �� );

notify( v2 );

��

}

};

B3

e2

Design hierarchy:

behavior Design() {

int v1;

B1

b1 ( v1 );

B2B3 b2b3( v1 );

void main(void) {

b1.main();

b2b3.main();

}

};

The SpecC Methodology

behavior B2B3( in int v1 ) {

int

v2;

event e2;

B2 b2( v1, v2, e2 );

B3 b2( v1, v2, e2 );

void main(void) {

par {

b2.main(); b3.main();

}

}};

behavior B3( in int

v1,

in int

v2,

in event e2) {

void main(void) {

��

wait( e2 );

f3( v1, v2, ��);

��

}

};

Copyright ?2001 A. Gerstlauer

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SpecC Methodology Tutorial

Specification Model Example (2)

? Message-passing communication

? Abstract communication

? Encapsulate communication

B2

B3

C2

Blocking, unbuffered message-passing channel:

interface Isend {

void send( void *d, int size );

};

interface Irecv {

void recv( void *d, int size );

};

behavior B3( in int v1,

IRecv c2) {

void main(void) {

��

c2.recv( &v2, sizeof(v2) );

f3( v1, v2, ��);

��

}

};

behavior B2B3( in int v1 ) {

ChMP c2();

B2

b2( v1, c2 );

B3

b3( v1, c2 );

void main(void) {

par {

b2.main(); b3.main();

}

}};

channel ChMP() implements ISend, IRecv {

void send( void *d, int size ) { �� }

void recv( void *d, int size ) { �� }

};

The SpecC Methodology

behavior B2( in int v1,

ISend c2) {

void main(void) {

��

v2 = f2( v1, �� );

c2.send( &v2, sizeof(v2) );

��

}

};

Copyright ?2001 A. Gerstlauer

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Architecture Exploration

? Component allocation / selection

Specification model

Architecture exploration

? Behavior partitioning

Architecture model

? Variable partitioning

Communication synthesis

Communication model

? Scheduling

Backend

Implementation model

The SpecC Methodology

Copyright ?2001 A. Gerstlauer

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SpecC Methodology Tutorial

Allocation, Behavior Partitioning

B1

B1

? Allocate PEs

PE1

PE2

v1

B2

? Partition behaviors

B3

? Globalize communication

C2

? Additional level of hierarchy to model PE structure

Copyright ?2001 A. Gerstlauer

The SpecC Methodology

9

Model after Behavior Partitioning

PE2

PE1

B1

B1

v1

B13snd

CB13

B2

B13rcv

B3

C2

B34rcv

CB34

B34snd

Synchronization behaviors:

behavior BSnd( ISend ch ) {

void main(void) {

ch.send( 0, 0 );

}};

The SpecC Methodology

behavior BRcv( IRecv ch ) {

void main(void) {

ch.recv( 0, 0 );

}};

Copyright ?2001 A. Gerstlauer

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