EE382V: Embedded System Design and Modeling

EE382V: Embedded Sys Dsgn and Modeling

EE382V: Embedded System Design and Modeling

Lecture 9 ? Computation Modeling & Refinement

Andreas Gerstlauer

Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu

Lecture 9

Lecture 9: Outline

? Processor layers ? Application ? Task/OS ? Firmware ? Hardware

? Processor synthesis ? Software synthesis ? Hardware synthesis

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EE382V: Embedded Sys Dsgn and Modeling

Lecture 9

System-On-Chip Environment (SCE)

Design Decisions

RTL DB

Specification

CCPPUU

Spec

System Design

(Specify-Explore-Refine)

PE/CE/Bus Models

TLTMLTMnLnMi

System models

Hardware Synthesis

Software Synthesis

SW DB

BB11 BB22

OOSS HHAALL DDrvrv ISISCRRPU

B1 B2

Coren Coren Coren Coren Core1 Coren OS + Drv

CPU Bus C1

CCoommppuuttaattiioonn mmooddeelliinnggaanndd

rreeffiinneemmeenntt

Mem

v1 v2

C2

C3

DSP B3

OS + Drv DSP Bus

C4

AArTcrLchhMnnn

B4 HW

B5 IP

HHWHWnW.nv.nv.v

RRTRTLTLnLn n

ISISSISSnSn n

Implementation Model

CCPCPUPUn.Unb.nibn.ibnin

ImImIpmplnplnln

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General Processor Micro-Architecture

? Basic computation component is a processor (PE) ? Programmable, general-purpose software processor (CPU) ? Programmable special-purpose processor (e.g. DSPs) ? Application-specific instruction set processor (ASIP) ? Custom hardware processor

PE

Bus interface

CLK

Controller

Status lines

Datapath

t

Control signals

Functionality and timing

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Computation Modeling (1)

? Structural RTL models

CPU

Controller

PC Fetch

IR

Decode

Load/store unit

CLK

Memory (data & progr.)

Datapath

Register file

ALU

HW

Controller

Next state logic

State

Output logic

Bus interface

CLK

Datapath

Register file

Memory

FU1

Software processor Sub-cycle accurate

Hardware processor

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Lecture 9

Computation Modeling (2)

? Behavioral RTL models (FSMD) ? Instruction-set simulation (ISS) models

? Purely functional or micro-architectural

Binary

App. RTOS HAL

ISS

CPU

HW

CPU_CLK

Instruction set simulation (ISS) Cycle or timing accurate

HW_CLK

FSMD

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Computation Modeling (3)

? Host-compiled modeling ? Compile and execute application natively

? Fast functional simulation

? Annotate application with target timing and power

? Accurate feedback

? Wrap with SLDL code for platform integration

? Add OS and processor models for integration into TLM backplanes

Fast and accurate simulation

Source: A. Gerstlauer. "Host-Compiled Simulation of Multi-Core Platforms," RSP10.

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Lecture 9

Computation Layers

CPU

Process B1() {

... waitfor(15000); ... waitfor(25000); ... };

P1 P2

OS HAL Drv ISR

Bus

Interrupts

? Application ? Process execution (C code) ? Execution timing

? OS & processor ? Operating system

? Real-time multi-tasking (RTOS model) ? Bus drivers (C code)

? Hardware abstraction layer (HAL)

? Interrupt handlers ? Media accesses

? Processor hardware

? Bus interfaces (I/O state machines) ? Interrupt suspension and timing

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Application Layer

? High-level, abstract programming model

? Hierarchical process graph

...

? ANSI C leaf processes ? Parallel-serial composition

CPU B1

... ...

? Abstract, typed inter-process

communication

B2

C1

B3

? Channels

C2

? Shared variables

Timed simulation of application functionality (SLDL)

? Back-annotate timing

? Estimation or measurement (trace, ISS)

Logical time

? Function or basic block level granularity

? Execute natively on simulation host

...

0 5 10

void f() {

waitfor(5);

...

? Discrete event simulator

}

? Fast, native compiled simulation

...

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Lecture 9

Automated Back-Annotation

? Back-annotation flow ? Compiler frontend

? Frontend optimizations

? Intermediate representation

? Optimized code ? IR to C conversion

? Re-targetable timing and power estimation

? Micro-architecture description language (uADL)

? Cycle-accurate ISS ? Reference power model

? Back annotation of estimates into IR

? Basic block level

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