EE382N: Embedded System Design and Modeling

EE382N: Embedded Sys Dsgn/Modeling

Lecture 8

EE382N:

Embedded System Design and Modeling

Lecture 8 �C Computation Modeling & Refinement

Andreas Gerstlauer

Electrical and Computer Engineering

University of Texas at Austin

gerstl@ece.utexas.edu

Lecture 8: Outline

? Processor layers

? Application

? Task/OS

? Firmware

? Hardware

? Processor synthesis

? Software synthesis

? Hardware synthesis

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Lecture 8

General Processor Micro-Architecture

? Basic computation component is a processor (PE)

? Programmable, general-purpose software processor (CPU)

? Programmable special-purpose processor (e.g. DSPs)

? Application-specific instruction set processor (ASIP)

? Custom hardware processor

Bus interface

PE

Controller

?t

Status lines

CLK

Datapath

Control signals

? Functionality and timing (and power and ��)

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Computation Modeling (1)

? Structural RTL models

Load/store unit

CPU

Controller

PC

Fetch

CLK

Datapath

Memory

(data &

progr.)

Register

file

Bus interface

HW

Controller

Next

state

logic

CLK

Datapath

Register

file

Memory

State

IR

ALU

Decode

Software processor

Output

logic

FU1

Hardware processor

? Sub-cycle accurate

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Lecture 8

Computation Modeling (2)

Binary

? Behavioral RTL models (FSMD)

? Instruction-set simulation (ISS) models

? Purely functional (binary translation) [QEMU,��]

? Micro-architectural (RTL in C) [GEM5,��]

App.

RTOS

HAL

CPU

HW

ISS

CPU_CLK

HW_CLK

Instruction set simulation (ISS)

FSMD

? Cycle or timing accurate

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Computation Modeling (3)

? Host-compiled models

? Source-level application model

�C Compile & execute natively

�C Fast functional simulation

? Back-annotate timing and

other metrics

? Abstract OS and processor

models

? Transaction-level model

(TLM) backplane

? C-based discrete-event

simulation kernel

[SpecC,SystemC]

? Fast and accurate full-system simulation

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Lecture 8

Host-Compiled Computation Layers

Process B1()

{

��

waitfor(15000);

��

waitfor(25000);

��

};

? Application

? Process execution (C code)

? Execution timing

CPU

? OS & processor

? Operating system

P1

P2

OS

HAL Drv ISR

�C Real-time multi-tasking (RTOS model)

�C Bus drivers (C code)

? Hardware abstraction layer (HAL)

�C Interrupt handlers

�C Media accesses

? Processor hardware

Bus

Interrupts

�C Bus interfaces (I/O state machines)

�C Interrupt suspension and timing

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Application Layer

? High-level, abstract programming model

? Hierarchical process graph

�C ANSI C leaf processes

�C Parallel-serial composition

? Abstract, typed inter-process

communication

�C Channels

�C Shared variables

CPU

B1

B2

C1

��

��

��

B3

C2

? Timed simulation of application functionality

? Annotate timing, energy, ��

�C Granularity?

�C Compiler optimizations?

�C Dynamic architecture effects?

? Source profiling [SCE]

? Back-annotate from ISS

? Predict from host activity

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Logical time

...

void f() {

waitfor(5);

...

}

...

0

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EE382N: Embedded Sys Dsgn/Modeling

Lecture 8

Source-Level Back-Annotation

? Retargetable backannotation flow

? Intermediate

representation (IR)

a=b=c=0;

if(a ................
................

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