EE141 Fall 1999 - University of California, Berkeley

( tr,min + ti + tl,min (eq. 9.2) thold + ( tclk-Q + tsum (modified to include hold time . and to use the given quantities) 100 + 230 ( 300 + 50. 330 ( 350 TRUE (barely)... Thus, this circuit has no race problem . Lastly, we find the minimum clock perdiod. Note that the maximum logic delay is a single sum plus the delay of the carry chain. ................
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