AD1674* 12-Bit 100 kSPS A/D Converter
嚜瘸
FUNCTIONAL BLOCK DIAGRAM
12/8
CS
A
0
CE
R/C
REF OUT
AGND
A
AAAA
AA
A
AAAAAA
AA
CONTROL
10V
REF
CLOCK
12
COMP
20k
REF IN
5k
BIP OFF
20V
IN
10VIN
SAR
12
10k
10k
5k
DAC
IDAC
2.5k
2.5k
5k
SHA
REGISTERS / 3-STATE OUTPUT BUFFERS
FEATURES
Complete Monolithic 12-Bit 10 ms Sampling ADC
On-Board Sample-and-Hold Amplifier
Industry Standard Pinout
8- and 16-Bit Microprocessor Interface
AC and DC Specified and Tested
Unipolar and Bipolar Inputs
65 V, 610 V, 0 V每10 V, 0 V每20 V Input Ranges
Commercial, Industrial and Military Temperature
Range Grades
MIL-STD-883 and SMD Compliant Versions Available
12-Bit 100 kSPS
A/D Converter
AD1674*
12
STS
DB11 (MSB)
DB0 (LSB)
AD1674
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD1674 is a complete, multipurpose, 12-bit analog-todigital converter, consisting of a user-transparent onboard
sample-and-hold amplifier (SHA), 10 volt reference, clock and
three-state output buffers for microprocessor interface.
1. Industry Standard Pinout: The AD1674 utilizes the pinout
established by the industry standard AD574A and AD674A.
The AD1674 is pin compatible with the industry standard
AD574A and AD674A, but includes a sampling function while
delivering a faster conversion rate. The on-chip SHA has a wide
input bandwidth supporting 12-bit accuracy over the full
Nyquist bandwidth of the converter.
The AD1674 is fully specified for ac parameters (such as S/(N+D)
ratio, THD, and IMD) and dc parameters (offset, full-scale
error, etc.). With both ac and dc specifications, the AD1674 is
ideal for use in signal processing and traditional dc measurement applications.
The AD1674 design is implemented using Analog Devices＊
BiMOS II process allowing high performance bipolar analog circuitry to be combined on the same die with digital CMOS logic.
Five different temperature grades are available. The AD1674J
and K grades are specified for operation over the 0∼C to +70∼C
temperature range. The A and B grades are specified from
每40∼C to +85∼C; the AD1674T grade is specified from 每55∼C
to +125∼C. The J and K grades are available in both 28-lead
plastic DIP and SOIC. The A and B grade devices are available
in 28-lead hermetically sealed ceramic DIP and 28-lead SOIC.
The T grade is available in 28-lead hermetically sealed ceramic
DIP.
2. Integrated SHA: The AD1674 has an integrated SHA which
supports the full Nyquist bandwidth of the converter. The
SHA function is transparent to the user; no wait-states are
needed for SHA acquisition.
3. DC and AC Specified: In addition to traditional dc specifications, the AD1674 is also fully specified for frequency domain ac parameters such as total harmonic distortion,
signal-to-noise ratio and input bandwidth. These parameters
can be tested and guaranteed as a result of the onboard
SHA.
4. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges:
0 V to +10 V and 0 V to +20 V unipolar, 每5 V to +5 V and
每10 V to +10 V bipolar. The AD1674 operates on +5 V and
㊣ 12 V or ㊣ 15 V power supplies.
5. Flexible Digital Interface: On-chip multiple-mode
three-state output buffers and interface logic allow direct
connection to most microprocessors.
*Protected by U. S. Patent Nos. 4,962,325; 4,250,445; 4,808,908; RE30586 .
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD1674每SPECIFICATIONS
(TMIN to TMAX, VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%, VEE = 每15 V 6 10% or
DC SPECIFICATIONS 每12 V 6 5% unless otherwise noted)
Parameter
Min
RESOLUTION
12
AD1674J
Typ
Min
AD1674K
Typ
Max
12
12
Unit
Bits
㊣1
INTEGRAL NONLINEARITY (INL)
DIFFERENTIAL NONLINEARITY (DNL)
(No Missing Codes)
Max
㊣ 1/2
12
LSB
Bits
UNIPOLAR OFFSET 1 @ +25∼C
㊣3
㊣2
LSB
BIPOLAR OFFSET1 @ +25∼C
㊣6
㊣4
LSB
0.25
% of FSR
+70
∼C
FULL-SCALE ERROR1, 2 @ +25∼C
(with Fixed 50 ? Resistor from REF OUT to REF IN)
TEMPERATURE RANGE
0.1
0
0.25
+70
0.1
0
TEMPERATURE DRIFT 3
Unipolar Offset2
Bipolar Offset2
Full-Scale Error2
㊣2
㊣2
㊣6
㊣1
㊣1
㊣3
LSB
LSB
LSB
POWER SUPPLY REJECTION
VCC = 15 V ㊣ 1.5 V or 12 V ㊣ 0.6 V
VLOGIC = 5 V ㊣ 0.5 V
VEE = 每15 V ㊣ 1.5 V or 每12 V ㊣ 0.6 V
㊣2
㊣ 1/2
㊣2
㊣1
㊣ 1/2
㊣1
LSB
LSB
LSB
+5
+10
+10
+20
Volts
Volts
Volts
Volts
7
14
k?
k?
+5.5
+16.5
每11.4
Volts
Volts
Volts
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
POWER SUPPLIES
Operating Voltages
VLOGIC
VCC
VEE
Operating Current
ILOGIC
ICC
IEE
每5
每10
0
0
3
6
+4.5
+11.4
每16.5
POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output Current (Available for External Loads) 4
(External Load Should Not Change During Conversion
5
10
9.9
+5
+10
+10
+20
每5
每10
0
0
7
14
3
6
+5.5
+16.5
每11.4
+4.5
+11.4
每16.5
5
10
5
10
14
8
14
18
5
10
14
8
14
18
mA
mA
mA
385
575
385
575
mW
10.0
10.1
2.0
10.0
10.1
2.0
Volts
mA
9.9
NOTES
1
Adjustable to zero.
2
Includes internal voltage reference error.
3
Maximum change from 25∼C value to the value at T MIN or TMAX.
4
Reference should be buffered for ㊣ 12 V operation.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
每2每
REV. C
AD1674
Parameter
Min
RESOLUTION
12
AD1674A
Typ Max
12
BIPOLAR OFFSET @ +25∼C
FULL-SCALE ERROR1, 2 @ +25∼C
(with Fixed 50 ? Resistor from REF OUT to REF IN)
0.1
每40
AD1674T
Typ Max
Unit
Bits
㊣ 1/2
㊣ 1/2
12
1
Min
12
㊣1
㊣1
UNIPOLAR OFFSET 1 @ +25∼C
TEMPERATURE RANGE
AD1674B
Typ Max
12
INTEGRAL NONLINEARITY (INL)
DIFFERENTIAL NONLINEARITY (DNL)
(No Missing Codes)
Min
㊣ 1/2
㊣1
12
LSB
LSB
Bits
㊣2
㊣2
㊣2
LSB
㊣6
㊣3
㊣3
LSB
0.125
% of FSR
+125
∼C
0.25
+85
0.1
每40
0.125
+85
0.1
每55
TEMPERATURE DRIFT 3
Unipolar Offset2
Bipolar Offset2
Full-Scale Error2
㊣2
㊣2
㊣8
㊣1
㊣1
㊣5
㊣1
㊣2
㊣7
LSB
LSB
LSB
POWER SUPPLY REJECTION
VCC = 15 V ㊣ 1.5 V or 12 V ㊣ 0.6 V
VLOGIC = 5 V ㊣ 0.5 V
VEE = 每15 V ㊣ 1.5 V or 每12 V ㊣ 0.6 V
㊣2
㊣ 1/2
㊣2
㊣1
㊣ 1/2
㊣1
㊣1
㊣ 1/2
㊣1
LSB
LSB
LSB
0
+5
+10
+10
+20
Volts
Volts
Volts
Volts
5
10
7
14
k?
k?
+5.5
+16.5
每11.4
Volts
Volts
Volts
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
POWER SUPPLIES
Operating Voltages
VLOGIC
VCC
VEE
Operating Current
ILOGIC
ICC
IEE
每5
每10
0
0
3
6
+4.5
+11.4
每16.5
POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output Current (Available for External Loads) 4
(External Load Should Not Change During Conversion
REV. C
5
10
9.9
+5
+10
+10
+20
每5
每10
0
0
7
14
3
6
5
10
+5.5 +4.5
+16.5 +11.4
每11.4 每16.5
+5
+10
+10
+20
每5
每10
0
7
14
3
6
+5.5 +4.5
+16.5 +11.4
每11.4 每16.5
5
10
14
8
14
18
5
10
14
8
14
18
5
10
14
8
14
18
mA
mA
mA
385
575
385
575
385
575
mW
10.0
10.1
2.0
10.0
10.1
2.0
10.0
10.1
2.0
Volts
mA
每3每
9.9
9.9
AD1674每SPECIFICATIONS
AC SPECIFICATIONS
(TMIN to TMAX, with VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%, VEE = 每15 V 610% or
每12 V 6 5%, fSAMPLE = 100 kSPS, fIN = 10 kHz, stand-alone mode unless otherwise noted)1
Parameter
Min
Signal to Noise and Distortion (S/N+D) Ratio2, 3
AD1674J/A
Typ
Max
69
4
70
Min
AD1674K/B/T
Typ
Max
70
Units
71
dB
Total Harmonic Distortion (THD)
每90
每82
0.008
每90
每82
0.008
dB
%
Peak Spurious or Peak Harmonic Component
每92
每82
每92
每82
dB
Full Power Bandwidth
Full Linear Bandwidth
1
500
Intermodulation Distortion (IMD)5
Second Order Products
Third Order Products
每90
每90
SHA (Specifications are Included in Overall Timing Specifications)
Aperture Delay
Aperture Jitter
Acquisition Time
50
250
1
1
500
MHz
kHz
每80
每80
每90
每90
每80
每80
dB
dB
50
250
1
ns
ps
?s
(for all grades TMIN to TMAX, with VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%,
EE = 每15 V 6 10% or 每12 V 6 5%)
DIGITAL SPECIFICATIONS V
Parameter
LOGIC INPUTS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current (VIN = 5 V)
IIL
Low Level Input Current (VIN = 0 V)
CIN
Input Capacitance
LOGIC OUTPUTS
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOZ
High-Z Leakage Current
COZ
High-Z Output Capacitance
Test Conditions
Min
Max
Units
VIN = VLOGIC
VIN = 0 V
+2.0
每0.5
每10
每10
VLOGIC +0.5 V
+0.8
+10
+10
10
V
V
?A
?A
pF
+0.4
+10
10
V
V
?A
pF
IOH = 0.5 mA
IOL = 1.6 mA
VIN = 0 to VLOGIC
+2.4
每10
NOTES
1
fIN amplitude = 每0.5 dB (9.44 V p-p) 10 V bipolar mode unless otherwise noted. All measurements referred to 每0 dB (9.997 V p-p) input signal unless
otherwise noted.
2
Specified at worst case temperatures and supplies after one minute warm-up.
3
See Figures 12 and 13 for other input frequencies and amplitudes.
4
See Figure 11.
5
fa = 9.08 kHz, fb = 9.58 kHz with f SAMPLE = 100 kHz. See Definition of Specifications section and Figure 15.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
每4每
REV. C
AD1674
SWITCHING SPECIFICATIONS
(for all grades TMIN to TMAX with VCC = +15 V 6 10% or +12 V 6 5%,
VLOGIC = +5 V 610%, VEE = 每15 V 6 10% or 每12 V 6 5%; VIL = 0.4 V,
VIH = 2.4 V unless otherwise noted)
CONVERTER START TIMING (Figure 1)
Parameter
Conversion Time
8-Bit Cycle
12-Bit Cycle
STS Delay from CE
CE Pulse Width
CS to CE Setup
CS Low During CE High
R/C to CE Setup
R/C Low During CE High
A0 to CE Setup
A0 Valid During CE High
J, K, A, B, Grades T Grade
Symbol Min Typ Max Min Typ Max Units
tC
tC
tDSC
tHEC
tSSC
tHSC
tSRC
tHRC
tSAC
tHAC
7
9
8
10
200
50
50
50
50
50
0
50
7
9
50
50
50
50
50
0
50
tHEC
CE
__
CS
8
?s
10 ?s
225 ns
ns
ns
ns
ns
ns
ns
ns
tHSC
tSSC
_
R/C
tSRC
tSAC
A0
tHRC
tHAC
tC
STS
READ TIMING〞FULL CONTROL MODE (Figure 2)
Parameter
J, K, A, B, Grades
T Grade
Symbol Min Typ Max Min Typ Max Units
Access Time
Data Valid After CE Low
tDD1
tHD
Output Float Delay
CS to CE Setup
R/C to CE Setup
A0 to CE Setup
CS Valid After CE Low
R/C High After CE Low
A0 Valid After CE Low
tHL5
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
75
150
252
203
75
252
154
150
50
0
50
0
0
50
50
0
50
0
0
50
tDSC
DB11 每 DB0
HIGH IMPEDANCE
Figure 1. Converter Start Timing
150 ns
ns
ns
150 ns
ns
ns
ns
ns
ns
ns
CE
__
CS
tHSR
tSSR
_
R/C
tSSR
A0
NOTES
1
tDD is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
2
0∼C to TMAX.
3
At 每40∼C.
4
At 每55∼C.
5
tHL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
tHRR
tSAR
tHAR
tHS
STS
tHD
DB11 每 DB0
HIGH
HIGH
DATA
VALID
IMPEDANCE
tDD
IMP.
tHL
Figure 2. Read Timing
Test
VCP
COUT
Access Time High Z to Logic Low
Float Time Logic High to High Z
Access Time High Z to Logic High
Float Time Logic Low to High Z
5V
0V
0V
5V
100 pF
10 pF
100 pF
10 pF
IOL
DOUT
VCP
COUT
IOH
Figure 3. Load Circuit for Bus Timing Specifications
REV. C
每5每
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