FLC_PHY1 Front-end chip



FLC_PHY1 Front-end chip

DATASHEET

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Table of content

1. General description 4

2. One channel Description 5

2.1. Preamplifier 5

2.2. Shaper 7

2.3. Direct output buffer 8

2.4. Track and hold 8

2.5. Multiplexed output buffer 9

2.6. Multiplexer description 9

3. Pin definition 11

4. Characteristics & measurement 13

4.1. DC levels 13

4.2. Crosstalk 14

4.3. Noise 15

4.4. Transient 16

4.5. Linearity 18

4.6. Pedestal 19

5. Annex 1 - Bias of FLC_PHY1 20

6. Annex 2 - Preamplifier schematic 21

7. Annex 3 – Shaper schematic 22

8. Annex 4 – Layout 23

Table of figures

Figure 1 - General block schema of FLC_PHY1 4

Figure 2- Block schema of one channel 5

Figure 3 - input charge preamplifier schema 5

Figure 4 - first stage of charge preamplifier 6

Figure 5 - preamplifier resistor feedback 7

Figure 6 - CRRC shaper schematic 7

Figure 7 - Block diagram of the track and hold 8

Figure 8 - Block diagram of the shift register 9

Figure 9 - Chronogram of the multiplexed readout 10

Figure 10 - FLC_PHY1 pinout 11

Figure 11 - Signal, noise and buffer noise versus Tp, no input capacitance 15

Figure 12 - Equivalent Noise Charge (in e- ) versus Tp, for different Cd 16

Figure 13 - Noise versus first stage preamp bias current 16

Figure 14 - Transient preamplifier output versus compensation capacitor 17

Figure 15 - Transient shaper output 18

Figure 16 - Linearity measurement on FLC_PHY1 18

Figure 17 - Pedestal dispersion on multiplexed output 19

Table 1- Compensation capacitance values 6

Table 2 - Pin description 12

Table 3 - FLC_PHY1 bias DC levels 13

Table 4 - Crosstalk measurement on FLC_PHY1 15

Table 5 - Rise time versus compensation switches 17

Equation 1 - Shaper transfer function 8

General description

The FLC_PHY1 Front-end chip is an 18-channel charge input front end circuit. It provides a shaped signal proportional to the input charge

Each channel is made of a charge preamplifier followed by a shaping filter using a CRRC structure. The FLC_PHY1 chip also embed a track & hold device driving a single multiplexed output.

The bias of each stage is common for every channel.

Figure 1 is a simplified schema block of the whole chip.

Figure 1 - General block schema of FLC_PHY1

One channel Description

Figure 2- Block schema of one channel

As shown on Figure 2, a channel is made of two stages (preamplifier and shaper) before being split in either the direct output or the Track & Hold and Multiplexed output. Each functional block will be described in detail below

1 Preamplifier

The input charge preamplifier is made of three stages as shown on Figure 3.

Figure 3 - input charge preamplifier schema

The first stage of that preamplifier is a common source transistor biased by a current source made of two NMOS transistor connected as a current mirror.

It is recommended to flow at least 500µA in the input PMOS to reduce series noise by increasing the PMOS gm. That means Vbiasi_pa should be connected to the high supply rail with a resistor smaller than 10kΩ (typ. 8.2kΩ for Ids=500µA or 4.3 kΩ for Ids=1mA).A compromise have to be done at this point by the designer between consumption and noise.

The noise can be reduce a little bit more by increasing the PMOS bulk voltage (pin Vdda). It is recommended to bias that bulk 2V higher than the high supply rail.

Figure 4 - first stage of charge preamplifier

The second stage is a common base bipolar transistor (NPN) in a cascode structure. The Vb pin allows to tune the input PMOS Vds. The Vbiasm_pa bias the bipolar transistor with a DC current.

After the second stage are the compensation capacitors that allows to slow the preamplifier down in case of oscillation, if the impedance on the input is not enough capacitive. The value of the compensation capacitance are given in Table 1.

|Capacitance |Value |

|Fixed |5pF |

|Switch 1 |2pF |

|Switch 2 |3pF |

Table 1- Compensation capacitance values

The third stage is a follower (common drain PMOS) biased by a current source (current mirror).

the feedback capacitor value is 1.5pF.

the resistor feedback is made of two unbalanced current mirror and a resistor (Figure 3).That makes the resistor virtually bigger.

The output transistor of the mirror is 50 times bigger than the input one, that means the current in the input line is 50 times lower. Considering there is two stage, the input current is 2500 smaller than the output one which is flowing in the feedback resistor. The resistor seen at the input of the preamp is then virtually 2500 bigger than its real value (36kΩ*2500=90MΩ, Figure 5).

Figure 5 - preamplifier resistor feedback

2 Shaper

The shaper is a CRRC filter using a two-stage gain amplifier (Figure 6). The first one is a high transconductance common source and the second a common drain follower. The transfer function is given by Equation 1.

Figure 6 - CRRC shaper schematic

Equation 1 - Shaper transfer function

The bias of the first stage is Vbiasi_sh.

The bias of the second stage is Vbiaso_sh.

A DC current of 25 to 50 µA is sufficient to bias the shaper. That means Vbiasi_sh as to be connected to lower supply rail with a 100 kΩ resistor. Vbiasi_sh as to be connected to upper supply rail with a 100 kΩ resistor too.

3 Direct output buffer

The direct output buffer is biased by the Vbias_out pin. Nominal DC current is between 50 and 100 µA. That is to say Vbias_out have to be connected to upper rail through a 50 to 100 kΩ resistor.

4 Track and hold

The track and hold allows to memorize an analogue value in a capacitance using a CMOS switch driven by the hold signal (pin H). That hold signal have to be synchronized with the peaking time of the shaper to ensure a maximum dynamic range and offset swing. The analogue value can then be red through the read CMOS switch. A follower forbids the charge of the capacitance to go away through the readout electronic. The value is then conserved during the reading.

The read switch is driven by a D latch cascaded as a shift register. That system permits to read sequentially the analogue value of the 18 channels with the multiplexed output. A block diagram of the track and hold is shown on Figure 7.

Figure 7 - Block diagram of the track and hold

5 Multiplexed output buffer

The output buffer is made of an OTA with a unit feedback on the negative input. The bias_buf pin is to bias the input differential peer of the OTA. 100 µA DC current is needed to bias that first stage. A 47 kΩ resistor to Vdd allows to obtain that current.

6 Multiplexer description

The multiplexer allows to serialize the 18 outputs. This is made by enabling the read of the track and hold (see Figure 7) of each channel sequentially one after another. The read of each channel is controlled by the output of a D-latch. To read sequentially outputs, it is needed to provide a “1” at the input of the shift register (pin R), which is the D of the channel 0. After a rising clock, the channel 0 is enable (i.e. readable on the output). The shift register input have then to be set to “0” before the next rising clock to avoid having several “1” propagating in the shift register, therefore several channel available at the output at the same moment. After a rising clock, the channel 0 will be disabled and the channel 1 will be enable as the output of the channel 1 D-latch will be “1”. The shift register will then shift the enabled output up to the 17th channel. When the 17th channel will be enabled, the output register (pin Q_R) will be up. That output allows to control that the shift register propagate properly the enabling value and permits to cascade several chip. The block diagram of the shift register is on Figure 8.The chronogram is available on Figure 9.

Figure 8 - Block diagram of the shift register

Figure 9 - Chronogram of the multiplexed readout

Pin definition

FLC_PHY1 is packaged in a 64-pin Ceramic Quad Flat Package (CQFP64).

Figure 10 - FLC_PHY1 pinout

|Pin number |Pin name |definition |

|64, 1–8, 10–18 |In 0 – in 17 |18 charge inputs |

|30, 32 – 48 |Out 0 – Out 17 |18 voltage outputs |

|9, 23, 29, 51 |Vss |Substrate bias |

|19, 24, 31 |Vdd |Circuit bias |

|63 |Vdda |Input transistor bulk bias |

|20,21 |SW1, SW2 |CMOS compensation capacitor switch |

| | |SW1 : 2 pF |

| | |SW2 : 3 pF |

|22 |Out_pa |Voltage output of the charge preamplifier (channel 17) |

|25 |Q_R |CMOS shift register output |

|26 |Bias_buf |Current bias of the multiplexed output buffer |

|27 |Out |Multiplexed output |

|28 |Bias_out |Current bias of the 18 output buffers |

|49 |Vbias_Cell |Current bias of the sample and hold circuit |

|50 |Rst_R |CMOS shift register reset |

|52 |R |CMOS shift register input |

|53 |Ck_R |CMOS shift register clock |

|54 |H |CMOS Hold command |

|55 |Vbiasi_sh |Input shaper stage current bias |

|56 |Vbiaso_sh |Output shaper stage current bias |

|57 |Vbiaso_pa |Output preamplifier stage current bias |

|58 |Vbiasm_pa |preamplifier middle current bias |

|59 |Vf |Feedback preamplifier leakage current bias (should be around 100nA) |

|60 |V_rf |Feedback resistor voltage bias |

|61 |Vb_casc |Base cascode transistor voltage bias |

|62 |Vbiasi_pa |Input preamplifier stage current bias |

Table 2 - Pin description

Characteristics & measurement

1 DC levels

All bias DC points are available on Table 3. It is good to notice that input DC is hardly measurable due to the high impedance of the preamplifier input. A good voltmeter have to be used (Internal resistance of voltmeter should be around 1 GΩ).Assuming a –5V/0V supply, the input should be around –1V. Preamplifier output should be between –2V and –1V depending on biasing current (biased by pin Vf). Output of the shaper is around –3.5V to –4V.

|Bias |Value |

| |Supply 0V/5V |Supply -5V/0V |

|Preamp|Vbiasi_pa |1.6V |-3.4V |

|lifier| | | |

| |Vbiasm_pa |3.6V |-1.4V |

| |Vbiaso_pa |3.6V |-1.4V |

| |Vb_casc |1.3V |-3.7V |

| |V_rf |1.7V |-3.3V |

| |Vf |4.3V |-0.7V |

|Shaper|Vbiasi_sh |3.6V |-1.4V |

| |Vbiaso_sh |0.8V |-4.2V |

|Buffer|V_bias_cell |3.5V |-1.5V |

|s | | | |

| |Bias_buf |-1.3V |-3.7V |

Table 3 - FLC_PHY1 bias DC levels

Using the bias detailed on annex, the FLC_PHY1 chip has a consumption of 140mW, thus 7.7mW per channel.

2 Crosstalk

Crosstalk have been measured on channel 5. A 1.2pC charge have been injected in channel 5. Channels 3,4,5,6 and 7 have been studied. The output signal and the value at peaking time have been measured and are available on Table 4.

|Channel|[pic] | |

|3 | |Signal magnitude @ peaking time : |

| | |329μV (0.04% of signal) |

|Channel|[pic] | |

|4 | |Signal magnitude @ peaking time : |

| | |1.538mV (0.19% of signal) |

|Channel|[pic] |HIT CHANNEL |

|5 | | |

| | |Injected charge : 1.2pC |

| | |Signal magnitude @ peaking time : |

| | |815.1mV (100% of signal) |

|Channel|[pic] | |

|6 | |Signal magnitude @ peaking time : |

| | |1.455mV (0.18% of signal) |

|Channel|[pic] | |

|7 | |Signal magnitude @ peaking time : |

| | |370μV (0.05% of signal) |

Table 4 - Crosstalk measurement on FLC_PHY1

3 Noise

Noise have been measured versus several parameters such as input capacitance (Cd), first stage preamp current, or peaking time (Tp).

Figure 11 shows signal and noise versus Tp. Signal is constant versus Tp except for small peaking time (i.e. high frequencies) due to preamp speed. Noise of preamp without Cd (called σ 0p on the graph) is decreasing vs Tp as it is dominated by serial noise. The test board buffer noise have been measured (σ buf on the graph) to ensure the buffer noise contribution is neglictible.

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Figure 11 - Signal, noise and buffer noise versus Tp, no input capacitance

Figure 12 represents Equivalent noise charge versus Tp for different input capacitance. These curves are far away from theoretic calculation. Further measurement and analysis will be proceeded to figure out behaviour of the FLC_PHY1.Series noise extracted from that measurement is 2.54 nV/sqrt(Hz). Theory give a series noise of 1nV/sqrt(Hz). Parallel noise is neglictible due to the big feedback resistor.

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Figure 12 - Equivalent Noise Charge (in e- ) versus Tp, for different Cd

Figure 13 gives the noise versus Tp for different input preamplifier stage current. The noise is decreasing while the current is increasing at Tp=200ns. That shows the compromise that designers have to make between consumption and noise.

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Figure 13 - Noise versus first stage preamp bias current

4 Transient

In that part, the transient output is studied. Figure 14 shows the preamplifier transient output versus compensation capacitance. The input charge is 75fC. The gain can be calculated, it is equal to 1.5pF that is the feedback capacitance. The measure is therefore good. The slow down of the preamplifier can be seen when the compensation capacitance increase. Table 5 details the rise time of the preamp for each compensation capacitance configuration with the same injection charge (75fC).

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Figure 14 - Transient preamplifier output versus compensation capacitor

|Switch 1 |Switch 2 |Rise time |

| | |10%-90% |

|0 |0 |14.4ns |

|0 |1 |18.6ns |

|1 |0 |21.9ns |

|1 |1 |27ns |

Table 5 - Rise time versus compensation switches

The transient measurement of shaper is on Figure 15. That measurement have been made on MUX output, on channel 15 with a 1.2pC injected charge.

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Figure 15 - Transient shaper output

5 Linearity

Linearity have been measured on multiplexed output. The measurement have been stopped when residual become bigger than 1%. That configuration gives a better than 1% linearity up to 3.2pC (that means 20 million e- ). Considering that there is 800 e- of noise with no input capacitance at shaper peaking time (see Figure 12). A dynamic range of 25000 so 14 bit. Linearity measurement is available on Figure 16.

Figure 16 - Linearity measurement on FLC_PHY1

6 Pedestal

Maximum pedestal dispersion is typically around 20mV. Standard deviation is around 5mV. Pedestal measurement is plot on Figure 17.

Figure 17 - Pedestal dispersion on multiplexed output

Annex 1 - Bias of FLC_PHY1

Measurements made for that datasheet have been done with following bias configuration.

Convention of bias : Vdd is upper rail and Vss is lower rail.

|Bias name |Bias configuration |Bias goal |Best supply decoupling |

|Vbiasi_pa |4.7k to Vdd |850µA |to Vdd |

|Vbiasm_pa |56k to Vss |70µA |to Vss |

|Vbiaso_pa |56k to Vss |70µA |to Vss |

|Vb_casc |1.3k to Vss |1.3V or |To rail set to ground |

| |3.7k to Vdd |-3.7V |(Vdd in datasheet meas.) |

|Vf |10M to Vss |4nA |to Vss |

|V_rf |10k to Vss |1.7V or |To rail set to ground |

| |20k to Vdd |-3.3V |(Vdd in datasheet meas.) |

|Vbiasi_sh |47k to Vss |100µA |To Vss |

|Vbiaso_sh |47k to Vdd |100µA |To Vdd |

|Bias_buf |47k to Vdd |100µA |To Vdd |

|Bias_out |47k to Vdd |100µA |To Vdd |

|Vbias_cell |150k to Vss |35µA |To Vss |

Annex 2 - Preamplifier schematic

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Annex 3 – Shaper schematic

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Annex 4 – Layout

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FLC_PHY1

CQFP 64 package

52

53

54

55

64

63

62

61

60

59

58

57

56

48

49

50

51

41

42

43

44

45

46

47

33

34

35

36

37

32

38

39

40

25

26

27

28

29

30

31

23

22

24

21

20

19

18

17

16

15

14

13

12

11

9

10

8

7

6

5

4

3

2

1

Out 16

Out17

Vdd

Vss

Bias_out

Out

Bias_buf

Q_R

Vdd

Vss

Out_pa

SW2

Vdd

In 17

SW1

In 13

In 14

In 15

In 12

Charge

Preamplifier

In 11

In 10

In 9

Vss

In 8

In 7

In 6

In 5

In 4

In 3

In 2

In 1

Ck_R

In 16

Vbias_cell

Vss

R

H

Vbiaso_sh

Vbiasi_sh

Vbiaso_pa

Vf

V_rf

Vb_casc

Vbiasi_pa

In 0

Vdda

Out 11

Out 14

Out 15

Out 13

Out 12

Out 7

Out 9

Out 10

Out 8

Out 5

Out 6

Out 4

Out 3

Out 2

CRRC

Shaper

Out 1

Out 0

Rst_R

Vbiasm_pa

Track & hold

MUX output

Direct output

INPUT

OUT

IN

Vdda

Vbiasi_pa

IN

Preamp out

Preamp in

I

I/50

I/2500

50

50

1

1

3636kΩ

OUT

IN

R2

C2

R1

C1

CMOS switch

[pic]

CMOS switch

To Multiplexed output buffer

D latch

Clock

Reset

D

Q

From shaper

Hold

Clock

Reset

To D of channel N+1

From Q of channel N-1

Ch.17

Ch.16

Ch.2

Ch.3

Ch.1

Ch.0

SROUT

OUT

SRIN

CLK

RST

Hold

READ17

READ16

READ2

READ1

READ0

SROUT

SRIN

D

D

Channel 0

D

RST

D

CLK

D

preamp

Shaper

Buffer

T&Hold

IN 0

OUT 0

OUT 1

IN 1

T&Hold

Buffer

Shaper

preamp

Channel 1

Channel 17

OUT 17

IN 17

T&Hold

Buffer

Shaper

preamp

Buffer

OUT MUX

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