Last (family) name:



Last (family) name: _________________________

First (given) name: _________________________

Student I.D. #: _____________________________

Circle section: Saluja Ramanathan

Department of Electrical and Computer Engineering

University of Wisconsin - Madison

ECE/CS 352 Digital System Fundamentals

Quiz #3 - SOLUTION

Thursday, November 6, 2003, 7:15 – 8:30 PM

Instructions:

1. Closed book examination.

2. No calculator, hand-held computer or portable computer allowed.

3. You must show your complete work. Points will be awarded only based on what appears in your answer book.

4. Five points penalty if you fail to enter name, ID# and instructor.

5. No one shall leave the room during the last 5 minutes of the examination.

6. Upon announcement of the end of the exam, stop writing on the exam paper immediately. Pass the exam to aisles to be picked up by a TA. The instructor will announce when to leave the room.

7. Failure to follow instructions may result in forfeiture of your exam and will be handled according to UWS 14 Academic misconduct procedures.

|Problem |Points |Score |

|1 |20 | |

|2 |10 | |

|3 |20 | |

|4 |10 | |

|5 |20 | |

|6 |10 | |

|7 |10 | |

|Total |100 | |

1. (20 points) Subtraction and decimal arithmetic

(a) (3 points) Number representation

Represent the numbers given in the table below as 8-bit signed numbers in the desired representation. The numbers are to have sign in the left most bit position. Complete the following table.

|Number |Signed magnitude |2’s complement |

|117 |0 1 1 1 0 1 0 1 |0 1 1 1 0 1 0 1 |

|89 |0 1 0 1 1 0 0 1 |0 1 0 1 1 0 0 1 |

|-117 |1 1 1 1 0 1 0 1 |1 0 0 0 1 0 1 1 |

|-89 |1 1 0 1 1 0 0 1 |1 0 1 0 0 1 1 1 |

(b) (12 points) Arithmetic

Perform the given operations in the table. For each case convert the numbers to proper representation and give the correct result in each representation. If the calculation produces an overflow in any of the representation indicate so and also show how you determined it to be an overflow.

|Problem |Signed magnitude |2’s complement |

| 117 | | 01110101 |

|+ ( - 89) | |+ 10100111 |

|28 | |1 00011100 |

| | |carry in = carry out |

| | |(in sign bit) |

| | |=> no overflow |

| - 117 | | 10001011 |

|+ 89 | |+ 01011001 |

|-28 | |11100100 |

| | | |

| | |no overflow |

| 117 | 0 1110101 add | 01110101 |

|- ( - 89) |+ 0 1011001 magnitudes |+ 01011001 |

|206 |1 1001110 |11001110 |

| |sign inversion => incorrect |carry in to sign bit but no carry out from |

|too large |result |sign bit |

| | |=> overflow |

(c) (2 points) 9’s complement

Find 9’s complement of the decimal number 2770

Ans: 7229

(d) (3 points) Decimal arithmetic

Use 10’s complement to perform the decimal subtraction below. You must show all your steps, answer alone will not be given any credit.

4579 - 1220

Ans: 4579 + 8780 = 13359

Carry out is dropped and the result is 3359

2. (10 points) Verilog

A logic circuit is given below.

[pic]

The Verilog description of the above circuit written by Mr. Buggy, barely familiar with the language, is given below. The description has numerous errors.

a) (4 points) Label all the unlabelled gates in the circuit above.

b) (6 points) Please point out to Mr. Buggy all the errors in the Verilog description by circling the errors and annotating as to what the error is. Note that the circuit given above is assumed to be the correct description.

module circuit_for_problem_2 (A, B, C , D, E, F);

input A, B, C, D, E;

output F;

wire w1, w2, w3, w4, w5, w6 ;

not

NO1(w1, B) ,

NO2(D, w2) ; Should be NO2 (w2, D);

nor Should be or

O1(w3, A, w1);

nand

NA1(w4, w3, E, C) ,

NA2(w2, C, w5) ; Should be NA2(w5, C, w2);

nand

NA3(w7, w4, w5) ; There is no wire w7, should be w6

and

A1(F, w6, B);

endmodule

3. (20 points) Waveforms

For the signals Q1, Q2, Q3, Q4, and Q5 draw the complete waveform. You will notice that we have used various types of storage devices and some of these are connected to the input signals while others are connected to the output of other storage devices. Assume that output of each storage element (each Q) has initial value of 0.

[pic]

[pic]

4. (10 points) State Table and State Diagram

(a) (9 points) Completing tables and diagrams

Partially completed state tables and state diagrams of a finite state machine, with 5 states and two inputs, are given blow. Complete both these using information from the two representations.

|PS |NS |Output |

| |0 0 |0 1 |1 0 |1 1 | |

|A |A |B |A |E |0 |

|B |B |D |B |C |1 |

|C |C |E |C |A |0 |

|D |D |C |D |E |1 |

|E |E |E |E |B |1 |

[pic]

(b) (1 point) Type of machine

Is the finite state machine given above a Mealy or a Moore machine? Circle the correct answer.

5. (20 points) Analysis

(a) (8 points) next state equations

Given a synchronous sequential circuit that contains two state variables A(t) and B(t). State variable A(t) is the output of a JK flip-flop, and state variable B(t) is the output of a T flip-flop. The flip-flop input equations to each of these flip-flops are

JA(t) = [pic]; KA(t) = X(t); and TB(t) =A(t) + X(t)

Derive the next state equations for A(t+1) and B(t+1) and write them in simplified SOP form.

[pic][pic]

[pic]

[pic]

[pic]

[pic]

[pic]

[pic]

| |A(t+1) = |[pic] |

|Answers: | | |

| |B(t+1) = |[pic] |

(b) (12 points) FF input equations and state table

A sequential circuit with three flip-flops is given below. Write the flip-flop input equations and the state table of this sequential circuit.

[pic]

FF input equations:

DA = x [pic]

DB = A

DC = B

|PS |NS |Output |

|A B C | | |

| |x = 0 |x = 1 | |

|0 0 0 |0 0 0 |1 0 0 |1 |

|0 0 1 |0 0 0 |0 0 0 |1 |

|0 1 0 |0 0 1 |1 0 1 |0 |

|0 1 1 |0 0 1 |0 0 1 |0 |

|1 0 0 |0 1 0 |1 1 0 |0 |

|1 0 1 |0 1 0 |0 1 0 |0 |

|1 1 0 |0 1 1 |1 1 1 |0 |

|1 1 1 |0 1 1 |0 1 1 |0 |

6. (10 points) Output sequence

State table of a sequential circuit with one input, X(t), and one output, Y(t), is given below.

|PS |NS |Output |

| |X = 0 |X = 1 |X = 0 |X = 1 |

|S0 |S3 |S1 |0 |0 |

|S1 |S2 |S0 |0 |1 |

|S2 |S0 |S3 |1 |0 |

|S3 |S0 |S2 |1 |1 |

a) (7 points) Output and states

Assume that initially the sequential circuit with above state table is in the state S0. Perform hand-simulation to fill in blanks in the table below.

|t |1 |2 |3 |

|2 input NAND |2 |2 |2 |

|3 input NAND |4 |1 |4 |

|D flip-flop |4 |2 |4 |

|JK flip-flop |4 |2 |4 |

[pic]

(a) (4 points) Delay computation

Compute the maximum combinational logic delay this circuit can have.

tCOMB = 2 + 2 + 2 + 4 + 2 = 12 ns

(b) (6 points) Operating frequency computation

What is the maximum frequency at which this circuit can operate. Assume that the setup time for the D flip-flop is 2 nano seconds and hold time is 0 nano second.

T = 4 + 12 + 2 = 18 ns

f = 1 / (18 x 10-9) Hz

Flip-Flop Characteristics Tables

|JK Flip Flop | |SR Flip-Flop |

|J |K |Q(t+1) | |S |R |Q(t+1) |

|0 |0 |Q(t) | |0 |0 |Q(t) |

|0 |1 |0 | |0 |1 |0 |

|1 |0 |1 | |1 |0 |1 |

|1 |1 |[pic] | |1 |1 |Indetminate |

|D Flip-Flop | |T Flip-Flop |

|D |Q(t+1) | |T |Q(t+1) |

|0 |0 | |0 |Q(t) |

|1 |1 | |1 |[pic] |

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