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left129396Request for Designs Response Worksheetin support ofRapid Assured Microelectronic Prototypes (RAMP) Phase 2020000Request for Designs Response Worksheetin support ofRapid Assured Microelectronic Prototypes (RAMP) Phase 2INSTRUCTIONS: Respondents must incorporate their proposed approach within the Response column as it relates to each item. Text contained within the No., Item and Description columns shall not be altered. 1. Respondent/Design InformationNo.ItemName & EmailResponse1.pany1.2Technical Program Manager1.3Design Lead2. General InformationNo.ItemDescriptionResponse (provide supporting documents as needed)2.1.ProductDescription of design2.2.ProgramDoD program that the design supports and the role of the chip in that program2.3.DesignDoes DIB have a path for development and deployment in a DoD program?2.ponentsListing of the major functional blocks in the design2.5.Quantifiable AssuranceRespondent(s) will work with RAMP to implement Quantifiable Assurance2.6.ConfidentialityAny ITAR or specific Security Requirements2.7.Physical Design ApproachRAMP support only desired or a turnkey approach desired2.8Foundry / Technology NodeIntel 22 FFL or GlobalFoundries 12LP2.9Delivery RequirementsExpected tapeout date for the chip3. SoC Features (Features listed below are desired, but not required for consideration) (if applicable)No.ItemDescriptionResponse (provide supporting documents as needed)3.1.Gate Count> 25M gates (NAND2 Equivalent) w/o memory3.2.Memory> 20Mb of SRAM (Static Random Access Memory)3.3.Processing UnitsAt least one controlling processing unit3.4.Clock SpeedClock speed > 1GHz3.5.High-Speed SerdesHigh speed SERDES (Serializer/Deserializer) IO (Input Output) operating above 12 Gb/sec3.mercial third-party intellectual property (IP)List any commercial third-party IP with short description(s)3.7.DoD-specific third-party IPList any DoD third-party IP with short description(s)3.8Production Test CapabilityList production test plan, including DFT (Design For Test), ATPG (Automatic Test Pattern Generation), designer will provide test vectors, test coverage4. Mixed Signal (Features listed below are desired, but not required for consideration) (if applicable)No.ItemDescriptionResponse (provide supporting documents as needed)4.1.Gate Count> 5M gates (NAND2 Equivalent) w/o memory4.2.Memory> 10Mb of SRAM memory4.3.Processing UnitsAt least one controlling processing unit4.4.Analog ElementsAt least 3 high-performance analog elements such as high-performance A/D (Analog/Digital), D/A (Digital/Analog), or SERDES IO4.mercial third-party intellectual property (IP)List any commercial third-party IP with short description(s)4.6.DoD-specific third-party IPList any DoD third-party IP with short description(s)4.7.Production Test CapabilityList production test plan, including DFT, ATPG, designer will provide test vectors, test coverage.5. Digital Design (Features listed below are desired, but not required for consideration) (if applicable)No.ItemDescriptionResponse (provide supporting documents as needed)5.1.Gate Count> 5M gates (NAND2 Equivalent) w/o memory5.2.Processing UnitsAt least one controlling processing unit5.mercial third-party intellectual property (IP)List any commercial third-party IP with short description(s)5.4.DoD-specific third-party IPList any DoD third-party IP with short description(s)5.5.Production Test CapabilityList production test plan, including DFT, ATPG, designer will provide test vectors, test coverage.6. Chiplet Features (Features listed below are desired, but not required for consideration) (if applicable)No.ItemDescriptionResponse (provide supporting documents as needed)6.1.Gate Count> 5M gates (NAND2 Equivalent) w/o memory6.2.Chiplet InterfacesUses AIB (Advanced Interface Bus) and/or AIB-2 interface protocols for IOs6.3.Additional chiplet interfacesList additional chiplet interfaces, if any6.4.SHIP Program InterfaceCoordinated with the SHIP program for packaging and test6.5.Production Test CapabilityList production test plan, including DFT, ATPG, designer will provide test vectors, test coverage. ................
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