ECE 3430 Exam 2



ECE 3430 Exam #2 (Fall 2014)Your Name: _________________Score: _____/123You may use the attached datasheets, a standard calculator, pencil, and scratch paper if you need it. Nothing else! For multiple-choice questions, circle the single correct answer to each question. For short answer questions, write your answer in the space provided on this exam paper.Upon coming out of the reset state, the MSP430 CPU jumps to what address to obtain the address of the first instruction code to execute? [2 points]The RAM interfaced to our MSP430 address and data bus begins at which of the following addresses? [2 points]0x00000x00200x02000xFFFEHow many writes and reads are performed to and from memory on the MSP430 address/data bus for the given assembly instruction: [2 points]xor.w 2(R4), 4(R5)Machine code: 0xE495 0x0002 0x0004Number of reads = _____Number of writes = _____In the lab, the interrupt vectors in the MSP430 are initialized: [2 points]At run-timeUsing CPU instructionsUsing assembler directivesUsing black magicShow the optimized machine code for the following instruction—making use of the constant generators: [2 points]and.w #4,R10__________Write the MSP430 assembly code required to add two 32-bit binary numbers located in memory locations 0x0220 and 0x0224 and store the 32-bit result in 0x0228. Use only 16-bit addition. Do not change the contents of the 32-bit memory locations 0x0220 and 0x0224. [5 points]For the questions 7-10, refer to the attached datasheets on digital I/O operation (pages 8.3-8.7).Write the single line of MSP430 assembly required to configure P1.7-P1.4 as inputs and P1.3-P1.0 as outputs. Make no assumption on the current directionality of any of the pins. [2 points]Write the two lines of MSP430 assembly required to configure P1.5 (previously configured as an input) to generate a falling-edge-triggered interrupt. Assume P1.7-P1.4 are configured as inputs (from the previous question). Assume the GIE flag in the SR is already set. [2 points]Write the single line of MSP430 assembly required to cause P1.3 and P1.2 to illuminate active-low interfaced LEDs without changing the state of P1.1 and P1.0. Assume the P1.3-P1.0 pins are already configured as outputs. [2 points]Write the two lines of MSP430 assembly required to cause R5 to hold the binary value 0x0010 if P1.4 is driven externally to logic 1 and R5 to hold the binary value 0 if P1.4 is driven externally to logic 0. [2 points]Write the two lines of MSP430 assembly required to divide the unsigned 16-bit value in R4 by 2. [2 points]Write the MSP430 code required to exchange the 16-bit contents of registers R7 and R8 using only the stack [4 points]:Write the MSP430 code required to exchange the 16-bit contents of registers R7 and R8 using no RAM for intermediate storage [4 points]:Which of your two implementations (in #12 and #13) would be faster to execute and why? [3 points]Why might you opt for the implementation in #13 over the implementation in #12 even if the system has plenty of memory and execution time is acceptably fast in both scenarios? In other words, what else do you gain besides speed and space? [2 points] Consider the following BCD addition operation. What would R4 contain after the following three lines of code complete? [4 points]mov#2000h,R4clrcdadd#8765h,R4R4 = _________Which of the following status register flags is not interrogated by any of the MSP430 jump instructions? [2 points]VZGIENCompare instructions (such as cmp): [2 points]Always use immediate addressing for the source operandMay change the destination operandCan change the state of status register bitsCan sometimes change the state of registers/accumulators in the programming model other than the status registerWhy is the jump range for any MSP430 jump instruction restricted: [4 points]What is the one 16-bit word that makes up the machine code for the following MSP430 assembly instruction? [2 points]mov@R5+,R6What are the two 16-bit words that make up the machine code for the following MSP430 assembly instruction? [2 points]bis.w#ABCDh,R8What is the one 16-bit word that makes up the machine code for the following MSP430 assembly instruction? [2 points]L1:jmpL1The code in #20 produces 2 read cycles across the memory address/data bus during execution. What data is transferred in each of the two read cycles? [4 points]Read 1: ______________________Read 2: ______________________The code in #21 also produces 2 read cycles across the memory address/data bus during execution. What data is transferred in each of the two read cycles? [4 points]Read 1: ______________________Read 2: ______________________Why doesn’t changing an “add.w” to “add.b” in MSP430 assembly result in quicker execution? After all, we would be doing 8-bit addition instead of 16-bit addition. During 8-bit addition, less data is required from the byte-addressable memory. [2 points]Which of the following is a signed jump instruction? [2 points]jhsjgejeqjloConsider the following code segment for questions 27-32.cmpR5,R4jgeS1S2:…jmpRJ1S1:…RJ1:…If R4 contained the value 0xF000 and R5 contained 0x0FFF, would the jge instruction be taken or skipped? [2 points]What would the value of the four main status register flags be after the cmp instruction completes—assuming the values from #27? [4 points]N = ____V = ____Z = ____C = ____What logic expression is evaluated by the jge instruction? [2 points]Show how your expression in #29 proves your conjecture in #27. [2 points]If the jhs instruction replaced the jge instruction, would the branch be taken or skipped? [2 points]Prove it using the flag values you calculated in #28 and the equation for jlo jhs. [2 points]To quickly multiply the contents of a register by 4, which MSP430 instruction should be used and how many times should it be used? [2 points]The stack is most accurately described as: [2 points]A non-volatile structureA first-in, first-out structureA first-in, last-out structureA last-in, last-out structureFor questions 35-36: Assume the stack pointer (SP) is initialized to 0x0400. Assume the following 16-bit values were pushed to the MSP430 stack in this order: 0x1122, 0x3344.What value would be held in the (stack pointer) SP register after the second push instruction? [2 points]If the CALL instruction were executed to call a subroutine, what value would be held in the SP register at the time the first instruction is executed in the subroutine? [2 points]Discuss briefly when using the BR instruction would be preferable over the use of the JMP instruction. Also briefly discuss when JMP would be preferable over the use of BR. [4 points]Explain briefly what happens when the RETI instruction is executed. [4 points]Which of the following is not a standard way to pass parameters in and out of a subroutine? [2 points]The stackuC control registersGlobal memoryProgramming model registersWhat bit in the status register (SR) must be set to enable all maskable interrupts and what instruction should be used to set it? [2 points]What is the interrupt vector table address for the Watchdog timer overflow interrupt? [2 points]Which of the following will not wake up an MSP430 microcontroller currently in the low-power mode level 4 (LPM4) state? [2 points]NMITimer_A interruptExternal port interruptResetAssume P1.0 is configured as an input and configured to trigger an interrupt on a falling edge. When a falling edge is detected, a flag is set in a register. What is the register name and what bit within that register is effected? [2 points]Assume a timer overflow interrupt has occurred (on Timer0_A). Write the minimum MSP430 interrupt service routine required to properly handle the timer overflow interrupt and return the machine to normal operation (until the next timer overflow event). Hint: Only two lines are needed. [4 points]What bit in the TACTL register must be set to enable timer interrupts? Precisely what value does the TAR (main timer) have to assume to cause the TAIFG flag to be set? [2 points]What would you consider to be the primary explanation of interrupt latency variation? In other words, why isn’t interrupt latency a constant? [4 points]What value would you write to the following TACTL register fields to configure the Timer_A block with the following characteristics?Use SMCLK to drive timer.Divide SMCLK by 4.Count in up/down count mode.Interrupt on timer (TAR) overflow. [5 points]TASSELx: ______IDx: _____MCx: _____TAIE: _____The end. ................
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