NXP Semiconductors Data Sheet: Technical Data ΣΔ S32R264K ...
• Harvard architecture with 64-bit bus for data instructions • 16 KB instruction cache and 16 KB data cache • 64 KB data local memory • with background load/store: backdoor access • 0-wait state for all read and 32/64-bit write accesses • Low number of wait states for backdoor accesses • Support for decorated storage ................
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