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In the figures above, (a) is a schematic of the 3D heterogeneous integration of Si PMOS transistors stacked on top of GaN NMOS transistors; (b) is a 3D cross-sectional view of the completed 3D transistor stack; (c) is a cross-section of a fabricated access via through the top device layer, to access the bottom GaN NMOS transistor; and (d) shows ... ................
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