P1010 QorIQ Integrated Processor Hardware

[Pages:105]Freescale Semiconductor Data Sheet: Advance Information

P1010 QorIQ Integrated Processor Hardware Specifications

Document Number: P1010EC Rev. 4, 05/2014

P1010

TePBGA1-425 19 mm x 19 mm

The following list provides an overview of the P1010 feature set:

? High-performance 32-bit Book E-enhanced core based on the Power Architecture technology: ? 36-bit physical addressing ? Double-precision floating-point support ? 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache ? 400- to 1000-MHz clock frequency

? 256-Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory

? Secure boot capability ? Three enhanced three-speed Ethernet controllers (eTSECs)

? 10/100/1000 Mbps support ? TCP/IP acceleration, quality of service, and

classification capabilities ? IEEE Std 1588TM support ? RGMII, SGMII ? eTSEC1 supports both RGMII/SGMII interfaces and

eTSEC2, eTSEC3 support SGMII interface ? High-speed interfaces supporting the following

multiplexing options: ? Two PCI Express 1.1 interfaces ? Two SATA Revision 2.0 interfaces ? Six lanes of high-speed serial interfaces to be shared

between PCI Express, SATA, and SGMII ? High-speed USB controller (USB 2.0)

? Host and device support ? On-chip USB 2.0 high-speed PHY ? Enhanced host controller interface (EHCI) ? ULPI interface ? Enhanced secure digital host controller (SD/MMC) ? Enhanced serial peripheral interface (eSPI) ? Integrated security engine (ULE CAAM) ? Protocol support includes DES, AES, RNG, CRC,

MDE, PKE, SHA, and MD5.

? DDR3/DDR3L SDRAM memory controller supports 32-bit without ECC and 16-bit with ECC

? Programmable interrupt controller (PIC) compliant with OpenPIC standard

? One 4-channel DMA controller ? Two I2C interfaces ? Four UART interfaces ? Two FlexCAN (version 2.0b) interfaces ? Integrated Flash controller (IFC) ? TDM ? 16 general-purpose I/O signals ? Operating temperature (Ta - Tj) range: 0?105 C (standard)

and ?40 C to 105 C (extended) ? 19 19 mm 425-ball wirebond TePBGA-1 package with

0.8 mm pitch

This document contains information on a new product. Specifications and information herein are subject to change without notice.

? Freescale Semiconductor, Inc., 2011-2014. All rights reserved.

Table of Contents

1 Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .4 1.1 Ball layout diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Pinout assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.1 Overall DC electrical characteristics . . . . . . . . . . . . . . .22 2.2 Power sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.3 Power-down Requirements . . . . . . . . . . . . . . . . . . . . . .27 2.4 Reset Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.5 Power-on ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.6 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.7 Input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.8 DDR3, and DDR3L SDRAM controller . . . . . . . . . . . . .33 2.9 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) .43 2.12 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.13 Integrated flash controller . . . . . . . . . . . . . . . . . . . . . . .58 2.14 Enhanced secure digital host controller (eSDHC) . . . .62 2.15 Programmable Interrupt Controller (PIC) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.16 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.17 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 2.19 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 2.20 TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 2.21 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . .74

2.22 PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.23 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3 Hardware design considerations . . . . . . . . . . . . . . . . . . . . . . 88 3.1 System clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.2 Supply power default setting . . . . . . . . . . . . . . . . . . . . 91 3.3 Power supply design and sequencing . . . . . . . . . . . . . 92 3.4 Decoupling recommendations . . . . . . . . . . . . . . . . . . . 93 3.5 SerDes block power supply decoupling

recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.6 Connection recommendations. . . . . . . . . . . . . . . . . . . 93 3.7 Pull-up and pull-down resistor requirements . . . . . . . . 93 3.8 Output buffer DC impedance . . . . . . . . . . . . . . . . . . . 94 3.9 Configuration pin muxing . . . . . . . . . . . . . . . . . . . . . . . 94 3.10 JTAG configuration signals . . . . . . . . . . . . . . . . . . . . . 95 3.11 Guidelines for high-speed interface termination . . . . . 97 3.12 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.1 Package parameters for P1010 . . . . . . . . . . . . . . . . . 100 4.2 Mechanical dimensions of P1010 WB-TePBGA . . . . 100 5 Security fuse processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.1 Part marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7 Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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This figure shows the major functional units within the P1010.

P1010

Security Acceleration

XOR

Secure Boot

Power Architecture e500 Core

32-Kbyte 32-Kbyte

L1

L1

I-Cache D-Cache

256-Kbyte L2 Cache

Coherency Module SyIs-CteamchBeus

TDM

3 x Gigabit Ethernet

On-Chip Network 2 x PCI Express 4 Ch DMA

Core

Acceleration

6-lane SERDES

Interface Figure 1. P1010 block diagram

DDR3/DDR3L SDRAM Controller

2 x DUART, 2 x I2C, Timers, Interrupt Control, SD/MMC, SPI, USB 2.0/ULPI 2xFlexCAN2.0b,GPIO

Integrated Flash Controller (IFC)

2 x SATA

P1010 QorIQ Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

3

Pin assignments and reset states

1 Pin assignments and reset states

1.1 Ball layout diagrams

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

A VSS MA_04 MA_07 MA_11 MA_06 MA_13 MA_15 MCS_2 VSS S2VDD SD2_ S2VDD SD2_ X2VDD VSS

UART_ UART_ SPI_ CAN1 CAN2 CTS_ CTS_ IIC1_ IIC2_ GPIO

A

_B

RX_1

RX_0

MOSI _TX _TX _0_B

1_B SDA SDA

_2

B MCS0_B NC

MA_03

VSS

MA_09 MA_02

VSS

SD2_ MCS_3 X2VDD S2VSS RXE_ S2VSS SD2_RX X2VSS X2VSS

_B

B

0_B

SPI_ MISO

VSS

CAN2 _RX

VSS IIC1_SCL GPIO _4

VSS GPIO_3 B

C MCKE_1MCS1_B MA_14 MBA_0 MBA_1 MA_08

MA_05 MDIC_1 X2VDD

SD2_ TX_1

S2VDD SD2_REF X2VDD SD2_TX S2VDD SPI_CLK OVDD

_CLK

_0

UART_ SOUT

_00

UART_ RTS_ B00

UART_ SOUT01

IIC2_ SCL

OVDD IRQ_3

C

D MA_10 VSS MA_00 MBA_2 MA_12

VSS

SD2_ MA_01 MDIC_0 X2VSS TX1_

1_B

S2VSS SD2_REF X2VSS SD2_TX S2VSS SPI_CS0 CAN1

_CLK_B

_0_B

_B

_RX

UART_ SIN00

UART_ RTS_ B01

IRQ_ OVDD OUT_ GPIO_01 GPIO_0

B

D

E MODT MODT MCKE VSS

_1

_0

_0

UART_ IRQ_1 GPIO_05HRESET E

SIN01

_B

F MRAS MCAS MCK_B MWE_B

_B

_B

SEE DETAIL A

SEE DETAIL B

RTC READY IRQ_2 IRQ_0 F

G MDQ VSS MDQ MCK

_10

_06

H MDQ

_12

MDQ MDQS VSS

_08

_0

GVDD

GVDD

GVDD

SD2_IMPSD2_PLL _CAL_TX _TPA

SD2_ SD2_PLL SD2_IMP AVDD _TPD _CAL_RX

VDD

VDD BVDD_ VSEL_0

GVDD

VDD

AVDD_ CORE

VDD

VDD

SD2_ AVSS

S2VDD

VDD

VDD

VDD

BVDD_ VSEL_1

OVDD TCK VSS TDD

G

SCAN TRST_B _MODE

_B

TDI

HRESET _REQ_B

H

J MDQS MDQ MDQS MDQ

_1

_14 _0_B _02

MVREF VDD

VSS VSS VSS

VSS VSS

VSS VSS

VDD VDD

USB OVDD VDD1_8 TMS USBVSS

J

K MDQS VSS MDQ_04 MDQ

_1_B

_00

GVDD VDD

VSS VSS VSS

VSS VSS

VSS VSS

VDD VDD

USB USB_V3DD3VDD1_8 USBVSS UDP

K

L MDQ MDM_1 MDQ_07 VSS

_9

M MDQ_15 MDQ_11 MDQ_01 MDM_0

GVDD VDD GVDD VDD

VSS VSS VSS VVSSSS VSS

VSS

TEMP_ VSS VSS VSS

VSS

VSS VSS VSS VSS

VDD USBVDD1 _0

VDD USBVDD1 _0

VUSB USBVDD3 CLMP USBVSS UDM

L

_3

IBIAS USBPHYUSBVSS _REXT USBVSS

M

_CLK

N MDQ_13 VSS MDQ_05 MDQ_03

GVDD VDD

VSS VSS VSS

VSS VSS

VSS VSS

VDD AVDD_ DDR

POVDD2 FA_ NC

NC

N

VDD

P MDQ_26 MDQ_30 MDQ_22 VSS

GVDD VDD

VSS VSS VSS

VSS VSS

VSS VSS

VDD AVDD_ PLAT

VSS

IFC_ AD_00 POVDD1 SYSCLK

P

R MDQ_28 MDQ_24 MDQ_18 MDQ_16

GVDD VDD

VSS VSS VSS

VSS VSS

VSS VSS

VDD VDD

IFC_AD _09

IFC_ AD_08

IFC_AD _01

VSS

R

T MDQS_3 VSS MDQS_2 MDQ_20

GVDD VDD

VDD

VDD X1VDD SD1_ S1VDD VDD AVSS

VDD

VDD BVDD

IFC_

IFC_

IFC_AD AD_10 IFC_AD ADDR

T

_11

_03

_02

U MDQ_ MDQ_31 MDQS VSS

_3_B

_2_B

V MDM_3 MDQ_25 MDQ_23 MDQ_17

LVDD LVDD VDD SD1_IMP SD1_PLL SD1_ SD1_PLLSD1_IMP VDD BVDD BVDD _CAL_RX _TPD AVDD _TPA _CAL_TX

SEE DETAIL C

SEE DETAIL D

IFC_

IFC_

BVDD AD_12 IFC_AD ADDR

U

_05

_04

IFC_AD _14

IFC_ AD_13

IFC_AD _07

IFC_ ADDR

_06

V

W MDQ_27 VSS MDM_2 MDQ_19

IFC_

IFC_AD ADDR_

_15

17

VSS

IFC_ ADDR

_16

W

Y MDQ_29 MDQ_21 SENSE

VSS

VSS

TSEC1_ GTX_

CLK125

TSEC1_ RX_CLK

S1VDD

SD1_RX _0

X1VDD

SD1_ TX_1

IFC_

S1VSS SD1_REF S1VDD SD1_TX X1VDD SD1_RX S1VSS CLK_0

_CLK_B

_2

_3

IFC_ RB_B

VSS

IFC_ IFC_

ADDR_ ADDR

21

_19

IFC_ ADDR

_18

Y

AA

NC

SENSE TSEC1_ TSEC1_ VDD GTX_CLKTXD_3

TSEC1_ TXD_2

EC_ MDC

IFC_

S1VSS SD1_RX X1VSS SD1_TX S1VDD SD1_REF S1VSS SD1_TX X1VSS SD1_RX S1VDD PERR_

_0_B

_1_B

_CLK

_2_B

_3_B

B

IFC_ BCTL

IFC_ IFC_CLE IFC_CS ADDR

_0_B _23

IFC_

ADDR _20

AA

AB

NC

VSS

TSEC1_ TSEC1_ RXD_2 RXD_1

LVDD

TSEC1_ S1VDD X1VDD RX_DV

SD1_ TX_0

S1VDD SD1_RX S1VDD SD1_RX S1VDD SD1_TX X1VDD

_1

_2

_3

S1VSS IFC_PAR _1

BVDD

IFC_OE IFC_CS _B _1_B

VSS

IFC_

ADDR _22

AB

AC

TSEC1_ EC_ TXD01 MDIO

TSEC1_ TSEC1_ RXD_3 RXD_0 TSEC1_ TSEC1_

VSS

X1VSS SD1_TX S1VSS SD1_RX S1VSS SD1_RX S1VSS SD1_TX X1VSS

TXD_0 TX_EN

0_B

_1_B

_2_B

_3_B

IFC_

VSS IFC_CLK IFC_PAR IFC_WP IFC_WE IFC_AVD ADDR

_1

_0

_B

_B

_24

AC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

P1010 QorIQ Integrated Processor Hardware Specifications, Rev. 4

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Freescale Semiconductor

Pin assignments and reset states

DETAIL A

1 2 3 4 5 6 7 8 9 10 11 12

A VSS MA_04 MA_07 MA_11 MA_06 MA_13 MA_15 MCS_2 VSS S2VDD SD2_ S2VDD

_B

RX_1

B MCS0_B NC

MA_03

VSS MA_09 MA_02

VSS

SD2_ MCS_3 X2VDD S2VSS RXE_ S2VSS

_B

B

C MCKE_1MCS1_B MA_14 MBA_0 MBA_1 MA_08 MA_05 MDIC_1 X2VDD SD2_ S2VDD SD2_REF

TX_1

_CLK

D MA_10 VSS MA_00 MBA_2 MA_12

VSS

SD2_

MA_01 MDIC_0 X2VSS TX1_ S2VSS SD2_REF

1_B

_CLK_B

E MODT MODT MCKE VSS

_1

_0

_0

F MRAS MCAS MCK_B MWE_B

_B

_B

G MDQ VSS MDQ MCK

_10

_06

SD2_IMPSD2_PLL SD2_ GVDD GVDD GVDD _CAL_TX _TPA AVDD

H MDQ

_12

MDQ MDQS VSS

_08

_0

AVDD_ GVDD VDD CORE VDD

VDD

SD2_ AVSS

J MDQS MDQ MDQS MDQ

_1

_14 _0_B _02

K MDQS VSS MDQ_04 MDQ

_1_B

_00

MVREF VDD VSS VSS VSS VSS GVDD VDD VSS VSS VSS VSS

L MDQ MDM_1 MDQ_07 VSS

_9

M MDQ_15 MDQ_11 MDQ_01 MDM_0

GVDD VDD VSS VSS VSS VVSSSS

GVDD VDD

TEMP_ VSS VSS VSS VSS

P1010 QorIQ Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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Pin assignments and reset states

DETAIL B

13 14 15 16 17 18 19 20 21 22 23

SD2_ X2VDD VSS

UART_ UART_ SPI_ CAN1 CAN2 CTS_ CTS_ IIC1_ IIC2_ GPIO

A

RX_0

MOSI _TX _TX _0_B

1_B SDA SDA

_2

SD2_RX X2VSS X2VSS SPI_ VSS CAN2 VSS IIC1_SCL GPIO VSS GPIO_3 B

0_B

MISO

_RX

_4

X2VDD SD2_TX S2VDD SPI_CLK OVDD _0

UART_ SOUT

_00

UART_ RTS_ B00

UART_ SOUT01

IIC2_ SCL

OVDD

IRQ_3

C

X2VSS SD2_TX S2VSS SPI_CS0 CAN1

_0_B

_B

_RX

UART_ SIN00

UART_ RTS_ B01

OVDD

IRQ_ OUT_ GPIO_01 GPIO_0

B

D

UART_ IRQ_1 GPIO_05HRESET E

SIN01

_B

RTC READY IRQ_2 IRQ_0 F

SD2_PLL SD2_IMP _TPD _CAL_RX

VDD

VDD

BVDD_ VSEL_0

S2VDD VDD VDD

VDD

BVDD_ VSEL_1

VSS VSS VSS VDD VDD

VSS VSS VSS VDD VDD

VSS VSS

VSS VSS VSS VSS

VDD USBVDD1 _0

VDD USBVDD1 _0

OVDD TCK VSS TDD

G

SCAN TRST_B _MODE

_B

TDI

HRESET _REQ_B

H

OVDD

USB VDD1_8

TMS

USBVSS

J

USB USB_V3DD3VDD1_8 USBVSS UDP

K

VUSB USBVDD3 CLMP USBVSS UDM

L

_3

IBIAS USBPHYUSBVSS _REXT USBVSS

M

_CLK

P1010 QorIQ Integrated Processor Hardware Specifications, Rev. 4

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Pin assignments and reset states

DETAIL C

N MDQ_13 VSS MDQ_05 MDQ_03

GVDD VDD VSS VSS VSS VSS

P MDQ_26 MDQ_30 MDQ_22 VSS R MDQ_28 MDQ_24 MDQ_18 MDQ_16

GVDD VDD VSS VSS VSS VSS GVDD VDD VSS VSS VSS VSS

T MDQS_3 VSS MDQS_2 MDQ_20

U MDQ_ MDQ_31 MDQS VSS

_3_B

_2_B

V MDM_3 MDQ_25 MDQ_23 MDQ_17

GVDD VDD

VDD

VDD X1VDD SD1_ AVSS

LVDD LVDD VDD SD1_IMP SD1_PLL SD1_ _CAL_RX _TPD AVDD

W MDQ_27 VSS MDM_2 MDQ_19

Y

MDQ_29 MDQ_21 SENSE VSS

VSS

TSEC1_ GTX_

CLK125

TSEC1_ RX_CLK

S1VDD

SD1_RX _0

X1VDD

SD1_ TX_1

S1VSS SD1_REF _CLK_B

AA

NC

SENSE TSEC1_ TSEC1_ VDD GTX_CLKTXD_3

TSEC1_ TXD_2

EC_ MDC

S1VSS SD1_RX X1VSS SD1_TX S1VDD SD1_REF

_0_B

_1_B

_CLK

AB

NC

VSS

TSEC1_ TSEC1_ RXD_2 RXD_1

LVDD

TSEC1_ S1VDD X1VDD RX_DV

SD1_ TX_0

S1VDD SD1_RX S1VDD _1

TSEC1_ EC_ TSEC1_ TSEC1_

AC

TXD01 MDIO RXD_3 RXD_0 TSEC1_ TSEC1_ VSS X1VSS SD1_TX S1VSS SD1_RX S1VSS

TXD_0 TX_EN

0_B

_1_B

1 2 3 4 5 6 7 8 9 10 11 12

P1010 QorIQ Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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Pin assignments and reset states

DETAIL D

VSS VSS

VSS VSS VSS VSS

VDD AVDD_ DDR

VDD AVDD_ PLAT

POVDD2 FA_ NC

NC

N

VDD

VSS

IFC_ AD_00 POVDD1 SYSCLK

P

VSS

VSS VSS

VDD VDD

IFC_AD _09

IFC_ AD_08

IFC_AD _01

VSS

R

S1VDD VDD VDD VDD BVDD

IFC_

IFC_

IFC_AD AD_10 IFC_AD ADDR

T

_11

_03

_02

SD1_PLLSD1_IMP VDD BVDD BVDD _TPA _CAL_TX

IFC_

IFC_

BVDD AD_12 IFC_AD ADDR

U

_05

_04

IFC_AD _14

IFC_ AD_13

IFC_AD _07

IFC_ ADDR

_06

V

IFC_

IFC_AD ADDR_

_15

17

VSS

IFC_ ADDR

_16

W

IFC_

S1VDD SD1_TX X1VDD SD1_RX S1VSS CLK_0

_2

_3

IFC_ RB_B

VSS

IFC_ IFC_

ADDR_ ADDR

21

_19

IFC_ ADDR

_18

Y

IFC_

S1VSS SD1_TX X1VSS SD1_RX S1VDD PERR_

_2_B

_3_B

B

IFC_ BCTL

IFC_ IFC_CLE IFC_CS ADDR

_0_B _23

IFC_

ADDR _20

AA

IFC_

SD1_RX S1VDD SD1_TX X1VDD S1VSS IFC_PAR BVDD IFC_OE IFC_CS VSS ADDR AB

_2

_3

_1

_B _1_B

_22

IFC_

SD1_RX S1VSS SD1_TX X1VSS VSS IFC_CLK IFC_PAR IFC_WP IFC_WE IFC_AVD ADDR AC

_2_B

_3_B

_1

_0

_B

_B

_24

13 14 15 16 17 18 19 20 21 22 23

P1010 QorIQ Integrated Processor Hardware Specifications, Rev. 4

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