ECE 3430 Exam 2 Solutions - University of Colorado ...



ECE 3430 Exam #2 Solutions (Fall 2009)

Your Name: Matt Laubhan

Score: 117/117

You may use your pink book (or printout of the pink book), calculator, pencil, and scratch paper if you need it. Nothing else! For multiple-choice questions, circle the single correct answer to each question. For short answer questions, write your answer in the space provided on this exam paper.

1) Upon coming out of the reset state, the HC11 jumps to which of the following addresses to obtain the upper 8-bits of the address containing the first opcode? [2 points]

a. $0040

b. $00FF

c. $E000

d. $FFFE

2) Where is the RAM located on our MicroStamps in the lab? [2 points]

Inside the HC11 microcontroller, outside of the CPU core. Located on the stamp-sized board that interfaces to the docking module. Due to ambiguity of this question, many answers are acceptable.

3) The EEPROM interfaced to the HC11 address and data bus is how big (on our MicroStamp)? [2 points]

a. 4 KB

b. 8 KB

c. 16 KB

d. 32 KB

4) The RAM interfaced to the HC11 address and data bus is mapped to which of the following address ranges? [2 points]

a. $0000 - $003F

b. $0040 - $00FF

c. $A000 - $BFFF

d. $E000 - $FFFF

5) The interrupt vectors in the HC11 are initialized using: [2 points]

a. At run-time

b. Using CPU instructions

c. Using assembler directives

d. Using black magic

6) True or False: It is possible to execute program code out of RAM. [2 points]

a. True

b. False

7) Write the HC11 assembly code required to add two 32-bit numbers located in memory locations $0040 and $0044 and store the 32-bit result in $0048. [5 points]

One way using 8-bit addition:

LDAA $43

ADDA $47 (note no carry in)

STAA $4B

LDAA $42

ADCA $46 (note the carry)

STAA $4A

LDAA $41

ADCA $45 (note the carry)

STAA $49

LDAA $40

ADCA $44 (note the carry)

STAA $48

8) What is the minimum number of address lines required to interface a 16Kx8 memory device to a byte-addressable microprocessor? [2 points]

14 lines

9) The HC11 built-in multiplication instruction is: [2 points]

a. Signed and capable of multiplying two 8-bit numbers

b. Unsigned and capable of multiplying two 8-bit numbers

c. Signed and capable of multiplying two 16-bit numbers

d. Unsigned and capable of multiplying two 16-bit numbers

10) The HC11 built-in integer division instruction is: [2 points]

a. Signed and capable of dividing two 8-bit numbers

b. Unsigned and capable of dividing two 8-bit numbers

c. Signed and capable of dividing two 16-bit numbers

d. Unsigned and capable of dividing two 16-bit numbers

11) True or False: It is possible to do floating point operations using the HC11? [2 points]

a. True

b. False

12) When performing packed BCD addition (as we discussed in class) on two 8-bit numbers, which criteria in the HC11 determines when a bias of 6 is added to a 4-bit nibble? [2 points]

a. The H flag in the CCR only

b. The C and H flags in the CCR only

c. The C and H flags in the CCR and whether the nibble is greater than 9

d. The C and H flags in the CCR and whether the nibble is greater than 10

13) When performing 8-bit packed BCD addition (as we discussed in class) using accumulator A, which HC11 instruction provides the correction to ensure the result is a valid BCD number? [2 points]

a. DAA

b. DES

c. ADDA

d. ADCA

14) Which of the following condition code register flags is not interrogated by any of the HC11 branch instructions? [2 points]

a. V

b. C

c. N

d. S

e. Z

15) Compare instructions (such as CMPA): [2 points]

a. Always use immediate addressing

b. Always use extended addressing

c. Can change the state of condition code register bits

d. Can sometimes change the state of registers/accumulators in the programming model other than the condition code register

16) The branching range of all HC11 branch instructions is: [2 points]

a. Backwards 128 bytes, cannot branch forward

b. Backwards 128 bytes, forward 127 bytes

c. Forward 127 bytes, cannot branch backwards

d. Backwards 127 bytes, forward 128 bytes

17) Write out the machine code (hand-assemble) the following code segment. Write the machine code to the right of the assembly code. Assume direct addressing on both the load and store instructions. [6 points]

MAIN: LDAB #$40 $C6 $40

INCB $5C

STAB $41 $D7 $41

BRA MAIN $20 $F9 (-7)

18) Fill in the blanks: During the execution of STY $ABCD on the HC11, ____ read cycles are generated on the address/data bus and ____ write cycles are generated on the address/data bus. [2 points]

4 read cycles (for the opcodes and operands) and 2 write cycles (for the store itself). 0 additional processing cycles. So, a total of 6 total cycles.

19) Which of the following is a signed branch instruction? [2 points]

a. BLT

b. BLO

c. BHI

d. BLS

Consider the following code segment and answer questions 20 and 21 (assume the E-clock frequency is 2 MHz). Also assume that $0200-$02FF is mapped to an external RAM.

Cycles:

LDAB $0200 4

CMPB $0201 4

BGT LABEL2 3

LABEL1: STAB $0202 4

BRA RJ1 3

LABEL2: ADDB #1 2

STAB $0202 4

RJ1: …

20) Assuming the BGT branch is taken, how long does it take the above code segment to complete (up to—but not including the instructions starting at RJ1)? [4 points]

4+4+3+2+4 = 17 cycles, 17 cycles * 500 ns/cycle = 8.5 microseconds

21) Assuming the BGT branch is not taken, how long does it take the above code segment to complete (up to—but not including the instructions starting at RJ1)? [4 points]

4+4+3+4+3 = 18 cycles, 18 cycles * 500 ns/cycle = 9 microseconds

22) What condition must be satisfied for BGT instruction to take the branch? [2 points]

Either of the following are acceptable answers:

1) The expression Z OR (N XOR V) = 0 must be satisfied.

2) The contents of $0200 must be greater than then contents of $0201 (when interpreted in the signed domain).

23) The purpose of using a compare instruction prior to executing a branch instruction is: [2 points]

a. To ensure memory is properly aligned for the branch instruction

b. To test a condition and adjust the CCR flags accordingly

c. To preserve the CCR prior to branch instruction execution

d. To force a change of contents to accumulators

24) Given the following set of instructions (and the effects each instruction has on the CCR), determine whether each branch instruction will take the branch or skip the branch. Check either Take Branch or Skip Branch for each branch instruction in the table below. [6 points, 1 point each]

| |S |X |

|BPL |X | |

|BLE | |X |

|BRN | |X |

|BNE |X | |

|BRA |X | |

|BHI |X | |

25) Assume accumulator A contains the value $01. After performing a logical shift left on accumulator A (LSLA) 8 times in a row, what would the state of the N, Z, and C flags in the CCR be? [2 points]

N = 0

Z = 1

C = 1

26) To quickly multiply the contents of accumulator D by 16, which HC11 instruction should be used and how many times should it be used? [2 points]

LSLD or ASLD (they are exactly the same in this case), 4 times in a row to multiply by 16.

27) The stack is most accurately described as: [2 points]

a. A non-volatile structure

b. A first-in, first-out structure

c. A last-in, last-out structure

d. A first-in, last-out structure

28) Assume the stack pointer (SP) is initialized to $00FF. Assume the following 8-bit values were pushed to the HC11 stack in this order: $77, $EF, $CD, $BB. If the TSX instruction is then executed (after all the pushing), what value would you find in the X index register? [2 points]

$00FC (pointing to the top element on the stack)

29) Approximately how long would it take the HC11 (if the E-clock frequency were 2 MHz) to execute the following code segment (assuming nothing interrupts this loop execution)? [4 points]

Cycles: Bytes:

LDY #535 4 4

LOOP: DEY 4 2

BNE LOOP 3 2

4 + 535(4+3) = 3749 cycles, 3749 cycles * 500 ns/cycle ~= 1.9 milliseconds

30) How many bytes of memory are consumed by the above chunk of code (in question #29)? [4 points]

4 + 2 + 2 = 8 bytes

31) If the stack pointer were initialized to $0700 and then the PSHX instruction were executed, to what address(es) would data be written? [2 points]

$06FF and $0700

32) Reconsider question #31 using our Microstamp from lab. If the following code was declared and we did the push instruction from question #31, could anything go wrong? If so what? [2 points]

ORG $06FC

JACK: RMB 2

JIM: RMB 2

Yes, the push (PSHX) would overwrite the lower byte of the JIM variable.

33) Discuss briefly when using the JSR instruction would be preferable over the use of the BSR instruction. Also briefly discuss when BSR would be preferable over the use of JSR. [4 points]

BSR supports only relative addressing and JSR can use direct, extended, or indexed. BSR can only branch to subroutines within range and JSR can jump to subroutines anywhere in memory.

When many subroutine invocations are called in the code and they are located close in program memory, the use of BSR would save memory and execution time.

If the subroutines are located far away (further than ~128 bytes away) in program memory (or their location is not known), JSR would be required.

34) Explain briefly what happens when the RTI instruction is executed. [4 points]

9 bytes of data are pulled from the top of the stack. These bytes are used to restore the state of the programming model—including the program counter (PC). By changing the program counter, the system can resume execution from the point of interrupt.

35) Which of the following is not a standard way to pass parameters in and out of a subroutine? [2 points]

a. The stack

b. Global memory

c. Programming model registers/accumulators

d. uC control registers

36) Assuming the HC11 I bit in the CCR is cleared, what happens to the X and I bits in the CCR when the physical IRQ pin is asserted low? [2 points]

a. Only I bit is set

b. Only X bit is set

c. Both X and I bits are cleared

d. Both X and I bits are set

37) Which of the following HC11 (our version of the HC11) maskable interrupt sources has the highest default priority? [2 points]

a. Timer overflow interrupt

b. Real time interrupt

c. Timer input capture channel 2

d. Timer output compare channel 1

38) Assume the stack looked like the following at the end of a subroutine you wrote (after pulling any data off the stack that you preserved during do-no-damage). If we used RTI rather than RTS to leave the subroutine, to what address would the program counter (PC) be set? [2 points]

M($00F7) = $C8

M($00F8) = $22

M($00F9) = $33

M($00FA) = $44

M($00FB) = $55

M($00FC) = $66

M($00FD) = $77

M($00FE) = $88

M($00FF) = $99

PC = $8899

39) Reconsider question #38. In addition to the subroutine not returning to the correct place, what else would happen as a consequence of using RTI instead of RTS to leave the ISR? [2 points]

The state of the entire programming model would be destroyed and the positive effects of using do-no-damage in the subroutine would have been lost.

40) Which of the following will not wake up an HC11 microcontroller currently in the stopped state (due to execution of STOP instruction)? [2 points]

a. IRQ

b. XIRQ

c. Timer overflow interrupt

d. Reset

41) Assume a timer overflow interrupt has occurred. Write the minimum HC11 interrupt service routine required to properly handle the timer overflow interrupt and return the machine to normal operation (until the next timer overflow event). [4 points]

LDAA #%10000000

STAA TFLG2 ($0025)

RTI

42) Assume real-time interrupts are enabled. If you needed to pulse an output pin of the microcontroller every 2 seconds, to what value would you set the RTR1 and RTR0 bits in the PACTL register and how many interrupts would you let lapse before you actually pulsed the output pin? [4 points]

RTR1 = 0 RTR0 = 0 # of interrupts = 2 secs/4.10 ms ~ 488

RTR1 = 0 RTR0 = 1 # of interrupts = 2 secs/8.19 ms ~ 244

RTR1 = 1 RTR1 = 0 # of interrupts = 2 secs/16.38 ms ~ 122

RTR1 = 1 RTR1 = 1 # of interrupts = 2 secs/32.77 ms ~ 61

For the chosen rate, an error on the interrupt count of + or - 1 is allowed.

43) Which of the following must be done to enable timer overflow interrupts in the HC11? [2 points]

a. TOI bit in TMSK2 = 0, I-bit in CCR = 0

b. TOI bit in TMSK2 = 1, I-bit in CCR = 0

c. RTII bit in TMSK2 = 0, I-bit in CCR = 0

d. RTII bit in TMSK2 = 1, I-bit in CCR = 0

44) What would you consider to be the primary explanation of interrupt latency? [2 points]

The fact that the hardware has to look up the ISR in the vector table and push the programming model to the stack before the first instruction in the ISR can execute.

45) Name one utility/debugging subroutine we use in the lab that uses global memory parameter passing. [2 points]

Subroutine name = DMPMEM, DMPRM

The end.

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