High Speed Fiber Optic Receiver - UC Santa Barbara
High Speed Fiber Optic Receiver
ECE 145C, Fall 2007
Karun Vijayraghavan and Matthew Guidry
Introduction
This project is to design a high speed fiber optic receiver chip. We created a circuit which does not fully function, due to incompatibilities between the demux and the limiting amplifier output. We can obtain a good eye pattern at 140Gbps from the receiver before the demultiplexer. We believe that this is mainly because of DC bias incompatibilities which we tried to resolve, but ultimately have not succeeded. The latch on its own performs well at 160Gbps.
Analysis
Note: All supporting circuit diagrams, plots, and hand analysis are in homework box.
TIA
Performs well up to 140Gbps. Zt of 45 ohms was obtained. We did not succeed in getting a higher transimpedance while keeping a fast rise/fall time and without introducing glitches or DC bias problems for following stages.
Limiting Amplifiers
Made of three identical cherry hooper circuits, which should each have a input and output bias voltage of -1.1v. We obtained a good eye pattern (more than 80%) up to 140Gbps. Cascading more than three led to a poor eye pattern because the DC bias would lower itself further down the chain.
Latch/Demux
A master slave latch was designed which gives a good eye pattern at 160Gbps with over 80% opening. One problem with it is noticeable glitches in the output voltage in response to changing inputs which should not affect the output voltage. Ultimately we were unable to successfully utilize it to demultiplex data from the limiting amplifier, due to DC bias issues, and possibly other reasons we have not fully identified.
Transmission lines
Due to a compact layout, transmission lines were only utilized in the clock buffer. All traces within the circuit were otherwise under 50um.
Layout
During the layout, the primary design goal was to make it is compact as possible to minimize transmission line effects, which should be simulated when wiring exceeds 50um length. In practice, this may not be the best method, because a more generic layout would be easier to change later.
Resistors were decided to always be 10um wide to make sure they would be able to handle the currents. Creating values is a simple matter of scaling length. The via/post structures for reaching either M1 or ground from collector metal were used frequently, so a separate design file was made to include them.
TIA
[pic]
Figure : TIA layout
Limiting Amplifiers
Limiting amplifiers were constructed as a chain of identical Cherry Hooper Amplifiers. One layout was repeated three times. Resistors were placed so that –Vee could easily reach the amplifier from either the top or the bottom.
[pic]
Demultiplexer
A layout for a single latch was created, then as a new design, two of these were connected in the master-slave configuration. Designed for data inputs to come in from the left, clock on the bottom, -Vee on the bottom, and data inputs on the top. Internal to the master-slave latch all traces are under 50um, so no transmission lines were simulated.
External to the latches is the clock buffer. Because the clock must travel a long distance, transmission lines must be used. It was constructed as a cherry-hooper split into its two stages, with transmission lines on the input and the output of the first gm block. The line from the second gm block to the latch clock is well under 50um. The line to the clock_bar input is, in total distance between transistor bases, over 50um. However, from the second gm block to each clock_bar input, each distance is less than 50um, so no transmission lines were simulated here.
[pic]
Single Latch
[pic]
Master-slave latch configuration
Overall Configuration
All of the smaller circuit elements were placed into an overall layout design. This design added interconnects between all circuits, the clock’s buffer, connections to RF pads, ground plane, and distribution of the –Vee power.
-Vee power was routed in metal 1 around the perimeter of the circuit, occasionally switching into collector metal to allow input and output signals through.
A ground plane in metal 3 was created.
All circuit interconnections except the mentioned clock inputs, and connections to pads, were kept well under 50um.
[pic]
Overall Layout
Transmission line simulations
With linecalc, it was found that for a microstrip model neglecting the dielectric material below metal, a 13um width gives 50 ohm characteristic impedance. All lines greater than 50um were made with that width.
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