ECE 3430 Exam 2 Solutions - University of Colorado ...



ECE 3430 Exam #2 Solutions (Fall 2014)Your Name: Matt LaubhanScore: 123/123You may use the attached datasheets, a standard calculator, pencil, and scratch paper if you need it. Nothing else! For multiple-choice questions, circle the single correct answer to each question. For short answer questions, write your answer in the space provided on this exam paper.Upon coming out of the reset state, the MSP430 CPU jumps to what address to obtain the address of the first instruction code to execute? [2 points]0xFFFEThe RAM interfaced to our MSP430 address and data bus begins at which of the following addresses? [2 points]0x00000x00200x02000xFFFEHow many writes and reads are performed to and from memory on the MSP430 address/data bus for the given assembly instruction: [2 points]xor.w 2(R4), 4(R5)Machine code: 0xE495 0x0002 0x0004Number of reads = 3 (to read in machine code) + 1 (reading source) + 1 (reading destination) = 5Number of writes = 1 (to write to the destination)In the lab, the interrupt vectors in the MSP430 are initialized: [2 points]At run-timeUsing CPU instructionsUsing assembler directivesUsing black magicShow the optimized machine code for the following instruction—making use of the constant generators: [2 points]and.w #4,R100xF22A (constant generator R2 is used with As = 10 to generate the constant 4)Write the MSP430 assembly code required to add two 32-bit binary numbers located in memory locations 0x0220 and 0x0224 and store the 32-bit result in 0x0228. Use only 16-bit addition. Do not change the contents of the 32-bit memory locations 0x0220 and 0x0224. [5 points]mov0x0220,R4add0x0224,R4movR4,0x0228mov0x0222,R4addc0x0226,R4movR4,0x022AThe ordering is required. The choice of register is arbitrary. R4-R15 are all valid choices. Adding .w after each instruction is optional—as the assembler chooses 16-bit by default.For the questions 7-10, refer to the attached datasheets on digital I/O operation (pages 8.3-8.7).Write the single line of MSP430 assembly required to configure P1.7-P1.4 as inputs and P1.3-P1.0 as outputs. Make no assumption on the current directionality of any of the pins. [2 points]mov.b #00001111b,&P1DIRAny number base can be used for the immediate value. The & is optional. The .b is required since the target register is only 8 bits wide.Write the two lines of MSP430 assembly required to configure P1.5 (previously configured as an input) to generate a falling-edge-triggered interrupt. Assume P1.7-P1.4 are configured as inputs (from the previous question). Assume the GIE flag in the SR is already set. [2 points]mov.b#00100000b,&P1IES or bis.b#00100000b,&P1IESmov.b#00100000b,&P1IEorbis.b#00100000b,&P1IEAny number base can be used for the immediate value. The & is optional. The .b is required since the target register is only 8 bits wide.Write the single line of MSP430 assembly required to cause P1.3 and P1.2 to illuminate active-low interfaced LEDs without changing the state of P1.1 and P1.0. Assume the P1.3-P1.0 pins are already configured as outputs. [2 points]bic.b#00001100b,&P1OUTorand.b#11110011b,&P1OUTAny number base can be used for the immediate value. The & is optional. The .b is required since the target register is only 8 bits wide.Write the two lines of MSP430 assembly required to cause R5 to hold the binary value 0x0010 if P1.4 is driven externally to logic 1 and R5 to hold the binary value 0 if P1.4 is driven externally to logic 0. [2 points]mov.b&P1IN,R5and.b#0x10,R5orbic.b#11101111b,R5Any number base can be used to specify the immediate values. The & is optional. The .b is required since the source register is only 8 bits wide.Write the two lines of MSP430 assembly required to divide the unsigned 16-bit value in R4 by 2. [2 points]clrcorrrc/rraR4rrcR4bic#8000h,R4You must use a rotate right with carry instruction and somehow ensure the shifted in bit on the left is zero—either by explicitly clearing the C flag before the rotate or explicitly clearing it after the rotate. The RRA preserves the left-most bit and can only be used if the left-most bit is cleared explicitly after the rotate.Write the MSP430 code required to exchange the 16-bit contents of registers R7 and R8 using only the stack [4 points]:push R7push R8pop R7pop R8All that is required is both registers are pushed to the stack and popped back off in exactly the same order.Write the MSP430 code required to exchange the 16-bit contents of registers R7 and R8 using no RAM for intermediate storage [4 points]:An intermediate swap register (other than R7 or R8) must be used. Here is one way using R9 as the swap register:mov R7, R9mov R8, R7mov R9, R8Which of your two implementations (in #12 and #13) would be faster to execute and why? [3 points]#13 should always be more efficient. Any answer involving the expense of RAM accesses or involvement of the memory address/data bus is acceptable. The push and pop instructions also have to additionally increment and decrement the stack pointer inside the CPU.Why might you opt for the implementation in #13 over the implementation in #12 even if the system has plenty of memory and execution time is acceptably fast in both scenarios? In other words, what else do you gain besides speed and space? [2 points] Power savings!Consider the following BCD addition operation. What would R4 contain after the following three lines of code complete? [4 points]mov#2000h,R4clrcdadd#8765h,R4R4 = 0x0765 (a carry out would be generated by the dadd instruction because the BCD result is 0x10765)Which of the following status register flags is not interrogated by any of the MSP430 jump instructions? [2 points]VZGIENCompare instructions (such as cmp): [2 points]Always use immediate addressing for the source operandMay change the destination operandCan change the state of status register bitsCan sometimes change the state of registers/accumulators in the programming model other than the status registerWhy is the jump range for any MSP430 jump instruction restricted: [4 points]The destination address is encoded as a jump distance (in words) relative to the current PC. Each jump instruction has a 10-bit, signed offset. So, the range is inherently limited to -512 words backwards to 511 words forward.What is the one 16-bit word that makes up the machine code for the following MSP430 assembly instruction? [2 points]mov@R5+,R6add @R5+,R60100 0101 0011 0110 = 0x4536 (instruction code only)I think I only added confusion in class when I said you could consider the “mov” instruction “add” instead. In hindsight that made no sense. However, if you changed “mov” to “add”, the first nibble of the single instruction code would simply change from 4 to 5…add @R5+,R60x5536What are the two 16-bit words that make up the machine code for the following MSP430 assembly instruction? [2 points]bis.w#ABCDh,R81101 0000 0011 1000 = 0xD038 (instruction code)0xABCD = (operand)What is the one 16-bit word that makes up the machine code for the following MSP430 assembly instruction? [2 points]L1:jmpL10011 1111 1111 1111 = 0x3FFF (instruction code only)The PC points to the next instruction code after this instruction code is read into the CPU. The PC must go back 1 word (2 bytes) to return to the same instruction and repeat indefinitely. The 10-bit signed offset is 111111111b (or -1) to indicate the PC is offset backwards one word.The code in #20 produces 2 read cycles across the memory address/data bus during execution. What data is transferred in each of the two read cycles? [4 points]Read 1: Reading the instruction code.Read 2: Reading the contents of the memory location contained in R5.The code in #21 also produces 2 read cycles across the memory address/data bus during execution. What data is transferred in each of the two read cycles? [4 points]Read 1: Reading the instruction code.Read 2: Reading the immediate value 0xABCD.Why doesn’t changing an “add.w” to “add.b” in MSP430 assembly result in quicker execution? After all, we would be doing 8-bit addition instead of 16-bit addition. During 8-bit addition, less data is required from the byte-addressable memory. [2 points]Because the data bus (if used) is 16-bit. The time it takes to fetch 16-bits of data and 8-bits of data is the same. If the data bus were 8-bit instead, the add.w would take longer since the 16-bit values in memory would have to be fetched piecewise.Which of the following is a signed jump instruction? [2 points]jhsjgejeqjloConsider the following code segment for questions 27-32.cmpR5,R4jgeS1S2:…jmpRJ1S1:…RJ1:…If R4 contained the value 0xF000 and R5 contained 0x0FFF, would the jge instruction be taken or skipped? [2 points]Because jge treats the contents of R4 and R5 as signed, it would skip the branch since 0xF000 (-4096) is not greater than or equal to 0x0FFF (+4095).What would the value of the four main status register flags be after the cmp instruction completes—assuming the values from #27? [4 points]N = 1V = 0Z = 0C = 1What logic expression is evaluated by the jge instruction? [2 points]N (XOR) V ?= 0Show how your expression in #29 proves your conjecture in #27. [2 points]You should plug in your values from #28 into the equation from #29 and prove that the expression is not satisfied.1 (XOR) 0 != 0If the jhs instruction replaced the jge instruction, would the branch be taken or skipped? [2 points]It would be taken since the jhs instruction treats the numbers as unsigned. 0xF000 (+61440) is now higher than 0x0FFF (+4095).Prove it using the flag values you calculated in #28 and the equation for jlo jhs. [2 points]C ?= 11 == 1To quickly multiply the contents of a register by 4, which MSP430 instruction should be used and how many times should it be used? [2 points]RLA, 2 times in a row to multiply by 4.RLC is acceptable only if the CLRC instruction precedes each RLC.The stack is most accurately described as: [2 points]A non-volatile structureA first-in, first-out structureA first-in, last-out structureA last-in, last-out structureFor questions 35-36: Assume the stack pointer (SP) is initialized to 0x0400. Assume the following 16-bit values were pushed to the MSP430 stack in this order: 0x1122, 0x3344.What value would be held in the (stack pointer) SP register after the second push instruction? [2 points]0x03FC (pointing to the top element on the stack)If the CALL instruction were executed to call a subroutine, what value would be held in the SP register at the time the first instruction is executed in the subroutine? [2 points]0x03FA (two less than the answer in #35). The CALL instruction pushes only the return address to the stack.Discuss briefly when using the BR instruction would be preferable over the use of the JMP instruction. Also briefly discuss when JMP would be preferable over the use of BR. [4 points]BR is an unconditional branch that has no distance restrictions. JMP is also an unconditional branch—but it has a distance restriction.BR, however, requires an operand separate from the instruction code to indicate the destination. The target for JMP is encoded as a 10-bit offset within the instruction code itself. So, BR will take longer to execute than JMP.Explain briefly what happens when the RETI instruction is executed. [4 points]This instruction is used to return from interrupt service routines. 4 bytes (2 words) of data are pulled from the top of the stack. These words represent the contents of the status register (SR) prior to the interrupt and the program counter (PC) of where the main code was executing at the time of the interrupt.Which of the following is not a standard way to pass parameters in and out of a subroutine? [2 points]The stackuC control registersGlobal memoryProgramming model registersWhat bit in the status register (SR) must be set to enable all maskable interrupts and what instruction should be used to set it? [2 points]GIE bit. Use the EINT instruction.What is the interrupt vector table address for the Watchdog timer overflow interrupt? [2 points]0xFFF4 (from the datasheet) Which of the following will not wake up an MSP430 microcontroller currently in the low-power mode level 4 (LPM4) state? [2 points]NMITimer_A interruptExternal port interruptResetAssume P1.0 is configured as an input and configured to trigger an interrupt on a falling edge. When a falling edge is detected, a flag is set in a register. What is the register name and what bit within that register is effected? [2 points]P1IFG is the register. Bit 0 is set to 1 when a falling edge is detected.Assume a timer overflow interrupt has occurred (on Timer0_A). Write the minimum MSP430 interrupt service routine required to properly handle the timer overflow interrupt and return the machine to normal operation (until the next timer overflow event). Hint: Only two lines are needed. [4 points]bic.w#TAIFG,TACTLorbic.w#1, TACTL (TACTL == TA0CTL)retiWhat bit in the TACTL register must be set to enable timer interrupts? Precisely what value does the TAR (main timer) have to assume to cause the TAIFG flag to be set? [2 points]TAIE (bit 1)When TAR == 0, the TAIFG flag is set.What would you consider to be the primary explanation of interrupt latency variation? In other words, why isn’t interrupt latency a constant? [4 points]The currently executing instruction must complete before the CPU can enter an ISR. Different instructions take different amounts of time to execute. What instruction is executing at the time of an interrupt can vary. Also, higher priority (non-maskable) interrupts or other maskable interrupts may have recently fired and these ISRs must complete first. Varying amounts of CPU activity can affect the interrupt latency for a given interrupt.What value would you write to the following TACTL register fields to configure the Timer_A block with the following characteristics?Use SMCLK to drive timer.Divide SMCLK by 4.Count in up/down count mode.Interrupt on timer (TAR) overflow. [5 points]TASSELx: 10IDx: 10MCx: 11TAIE: 1The end. ................
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