HW-AFX-COOL2-256MC
HW-AFX-SP3-1500 / 2000
Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation Platform
User Guide and Reference Manual
Revision 1.6
January 3, 2006
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This document describes the HW-AFX-SP3-1500 / 2000 development board provided by Nu Horizons Electronics Corp. No warranty is given for the suitability of this design for any purpose other than prototyping and functional operation. Nu Horizons Electronics assumes no liability with respect to the use of the board nor liability for the use of the circuitry inside the Xilinx FPGA. The information contained in this document is subject to change without notice.
Table of Contents:
1.0 Introduction 5
Figure1: Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation Board Block Diagram 6
2.0 Evaluation Board Contents 7
3.0 Board Overview 7
LEDs 7
Table 1: LED Pin Connections to XC3S1500 / 2000 8
Pushbuttons 8
Table 2: Pushbutton Pin Connections to XC3S1500 / 2000 8
4x24 Character LCD Display 8
Table 3: LCD PIN Connections – XC3S1500 / 2000 8
4x24 Character LCD Display Read/Write Timing Chart 9
Figure 2: 4x24 Character LCD Display Read/Write Waveforms 9
PLL Clock Multiplier 10
Figure 3: ICS511 PLL Clock Multiplier Circuit 10
Figure 4: U54 Oscillator Socket 10
Table 4: Clock PIN Connections – XC3S1500 / 2000 10
Table 5 – Clock Output Table 11
Programmable Frequency Synthesizer 11
Table 6: M Divide Function Table 11
Table 7: N Output Divider Function Table 11
Figure4: ICS84021 Frequency Divider 12
Table 8: ICS84201 Clock Signal – XC3S1500 / 2000 12
RS-232-C Interface 12
Table 9: RS-232 Port 1 Pins – XC3S1500 / 2000 12
Table 10: RS-232 Port 2 Pins – XC3S1500 / 2000 12
Figure 5: RS232 Port 1 & 2 13
Table 11: RS232 Speed Select Jumper Settings 13
CAN 2.0B High Speed Transceiver 13
Figure 6: CAN 2.0B Bus Controller & High-Speed Transceiver 14
Table 12: L9616 Connections 14
Table 13:J11 CAN ASC Settings 14
Figure 7: CAN Interface 15
PS2 Interface 15
Table14: PS2 Port Interface – XC3S1500 / 2000 15
Figure 8: PS2 Port Interface 15
14bit Linear CODEC 16
Figure9: STw5093 Circuit Diagram 16
Table 15: Audio CODEC FPGA Signal Connections – XC3S1500 / 2000 16
Analog to Digital Converter 17
Table16: LTC1865L ADC SPI Interface – XC3S1500 / 2000 17
Table 17: LTC1865L ADC Signal Input Header / Jumper Settings 17
Digital to Analog Converter 18
Table18: LTC1654 DAC SPI I/F 18
Table 19: LTC1654 DAC Signal Input Header 18
Table 20: LTC1654 DAC Signal Gain Settings 18
SDRAM Interface 19
Table 21: SDRAM PIN I/F 19
NBT SSRAM Interface (Alternative Memory – Not Included on standard build) 20
Table 22: SSRAM PIN I/F 20
Flash Interface 21
Table 23: Flash PIN I/F – XC3S1500 / 2000 21
Test Point Headers 3.3V 22
Table 24: J24 3.3V Test Point Header PIN Connections – XC3S1500 / 2000 22
Table 25: J25 3.3V Test Point Header PIN Connections – XC3S1500 / 2000 23
Table 26: J32 3.3V Test Point Header PIN Connections – XC3S1500 / 2000 23
Table 27: PD Test Points Connections 23
LVDS Test Point Header 24
Table 28: J23 LVDS PIN Connections 24
10/100 Ethernet Media Access Controller 25
Table 29: SMSC 91C111 FPGA Pin Connections – XC3S1500 / 2000 25
10/100 Ethernet Physical Interface 26
Table 30: ICS1893 Pin Connections – XC3S1500 / 2000 26
Linear Technology High Speed Analog to Digital Interface 26
Table 31: LTC High Speed ADC Evaluation Board Part Numbers 26
Figure 12: LTC Evaluation Board 27
Linear Technology High Speed ADC Interface Connections 27
Table32: J29 LTC ADC Interface – XC3S1500 / 2000 27
Figure 13: J29 Circuit Diagram 28
Intersil High Speed Digital to Analog Interface 29
Table 33: Intersil Evaluation Board Part Numbers 29
Intersil High Speed DAC Interface Connections 29
Table 34: J27 Intersil DAC Interface – XC3S1500 / 2000 29
Figure14: J27 Circuit Diagram 30
Table 35: J28 Intersil DAC Interface – XC3S1500 / 2000 30
Figure 15: J28 Circuit Diagram 31
Graphical LCD Interface 31
Figure 16: J31 Circuit Diagram 32
Table 36: J31 LCD I/F Connections – XC3S1500 / 2000 32
Agilent Soft Touch Probe Interface 33
Figure 17: Agilent E5394A Soft Touch Probe Connector Diagram 33
Programming Interface 34
Table 37: Cable III Interface 34
Table 38: Cable IV Interface 34
Operating and Storage Environments 34
Regulatory Compliance (FCC Part 15 Class B, and Part 68) 34
Scope
This document defines the configuration of jumpers and the function of various components of the baseline board level hardware elements that comprise the HW-AFX-SP3-1500 / 2000 evaluation platform.
Introduction
The Spartan3-1500 / 2000 evaluation platform is a very flexible testing platform that allows the engineer to evaluate the Xilinx XC3S1500 / 2000 FPGA in a typical application. Block diagram is provided, Figure 1.
The distinctive features of the board include.
• Based on the Spartan 3 - 1.5 Million Gate FPGA
o XC3S1500-4 FG676C
• 2 Channel A/D Converter
o Linear Tech LTC1865L
▪ 16bit 150Ksps
• 2 Channel D/A Converter
o Linear Tech LTC1654
▪ 14bit 8us Conversion Time
• 2 - 4M X 16 SDRAM – 128Mb
o ISSI42S16400
• 32Mb Flash 2Mb X 16
o ST M29W320DB
• 4 X 24 Character LCD Interface
• PS2 Port Interface
• 2 - RS232 Serial Ports
• CAN 2.0B Physical Layer
o ST L9616
• Graphics LCD Interface
o Logic Product Display Kit Compatible
• 10/100 Ethernet Phy.
o ICS1893BF
• 10/100 Ethernet MAC
o SMSC 91C111
• 16bit LVDS I/F with Clock & Control
• Audio Codec
o STw5093 14bit Linear CODEC
• ICS511 PLL Clock Multiplier
o 20MHz Crystal
• ICS84021 PLL Clock Multiplier
o 20MHz Clock Crystal
• 50 MHz clock Oscillator
o Secondary Oscillator Socket Provided
• XCF08 Platform Flash for Configuration
• 8 LED’s
• 4 Push Buttons
• 73 - 3.3V Test/Expansion Pin Headers
• Agilent E5404A Soft Touch Pro Probe
Applications:
• Microblaze Soft Processor Development
• DSP System Development
• Industrial Systems Development
• Universal Prototyping Platform
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Figure1: Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation Board Block Diagram
Evaluation Board Contents
• HW-AFX-SP3-1500 / 2000 Development Board
• Documentation CD
• AC Power Supply
Board Overview
Power Supply
The HW-AFX-SP3-1500 / 2000 board can be powered from an external power supply, two power connectors are provided. (J17 – DC Barrel Jack, J16 - Vertical Header 0.1’)
External power supply must reside between 6 and 9 Volts
Regulators on the board supply:
• 5.0V/750mA
• 3.3V/3A
• 2.5V /800mA– LVDS I/F
• 1.2V/2A - VccInt
• 1.8V / 2.5V/ 3.3V – 750mA Adjustable
• +12 & -12V /75mA
Power Status LED
There are two power status LEDs that provide status for the 3.3V and 3.3V ANA voltage levels.
LED9 – 3.3V ANA – Analog voltage level
LED11 – 3.3V Digital supply voltage.
LEDs
Eight LEDs are provided for display outputs. LED cathodes are driven directly from the FPGA via 470-ohm resistor, and the anodes are connected directly to 3.3V supply.
:
LED Position XC3S1500 / 2000 PIN
|LED 1 |M6 |
|LED 2 |M7 |
|LED 3 |M8 |
|LED 4 |N2 |
|LED 5 |N3 |
|LED 6 |N4 |
|LED 7 |N5 |
|LED 8 |N6 |
Table 1: LED Pin Connections to XC3S1500 / 2000
Pushbuttons
Four pushbuttons are provided for circuit input.
Pushbutton Position XC3S1500 / 2000 PIN
|PB_SW1 |W22 |
|PB_SW2 |W24 |
|PB_SW3 |W25 |
|PB_SW4 |W26 |
Table 2: Pushbutton Pin Connections to XC3S1500 / 2000
4x24 Character LCD Display
The HW-AFX-SP3-1500 / 2000 board includes a 4x24 Character LCD display. The LCD display has an integrated LCD controller/driver from Microtips Technology (MTC-S20400XFGNSAY). The following chart details the LCD connections to the XC3S1500 / 2000.
LCD PIN XC3S1500 / 2000
|LCD_RS |T19 |
|LCD_RW |T20 |
|LCD_EN |T21 |
|LCD_DATA0 |T22 |
|LCD_DATA1 |T23 |
|LCD_DATA2 |T25 |
|LCD_DATA3 |T26 |
|LCD_DATA4 |U20 |
|LCD_DATA5 |U22 |
|LCD_DATA6 |U23 |
|LCD_DATA7 |U24 |
|BACKL_ON |Y25 |
Table 3: LCD PIN Connections – XC3S1500 / 2000
4x24 Character LCD Display Read/Write Timing Chart
Figure 2: 4x24 Character LCD Display Read/Write Waveforms
PLL Clock Multiplier
The HW_AFX_SP3-1500 / 2000 Evaluation Platform board provides the user with a 20MHz clock crystal Y1 in conjunction with an ICS511 PLL clock multiplier for circuit evaluation. Also an 8-pin oscillator socket, U9, is also provided for customers to install their own clock oscillator.
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Figure 3: ICS511 PLL Clock Multiplier Circuit
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Figure 4: U54 Oscillator Socket
Clock Signal XC3S1500 / 2000 Pin
|PLL_CLK |AE14 |
|MAIN_CLK |AF14 |
Table 4: Clock PIN Connections – XC3S1500 / 2000
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Table 5 – Clock Output Table
Programmable Frequency Synthesizer
The Spartan 3 – 1500 / 2000 Evaluation Board utilizes the ICS84021 frequency synthesizer to supply the high frequency clock to the Intersil Digital to Analog converter evaluation board and the XC3S1500 / 2000 FPGA. The ICS84021 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the on chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 620MHz to 780MHz. The output of the M divider is also applied to the phase detector. The programmable features of the ICS84021 support a parallel input to program the M divider and N output divider. The M value and the required values of M0 through M8 are shown in table 6 and N0 – N1 values are shown in table 7.
VCO MHz M Divide M8-256 M7-128 M6-64 M5-32 M4-16 M3-8 M2-4 M1-2 M0-1
|625 |25 |0 |0 |0 |
|0 |1 |4 |155 |195 |
|1 |0 |5 |124 |156 |
|1 |1 |6 |103.3 |130 |
Table 7: N Output Divider Function Table
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Figure4: ICS84021 Frequency Divider
ICS84021 Clock Signal XC3S1500 / 2000 Pin
|PLL_CLK_FPGA |C14 |
Table 8: ICS84201 Clock Signal – XC3S1500 / 2000
RS-232-C Interface
The Spartan3 - 1500 / 2000 Evaluation Board uses two ST Microelectronics ST3237 level converters to generate the required RS-232-C voltage levels. Both interfaces are wired as DCE ports and have selectable speed jumper, figure 3 details the jumper and circuit. Pin definitions listed bellow in Table 6 & 7.
RS232 I/F XC3S1500 / 2000 PIN
|LV_RX_DATA |V20 |
|LV_TX_DATA |U26 |
|LV_RTS |U25 |
|LV_DCE_READY |V22 |
|LV_CTS |V21 |
Table 9: RS-232 Port 1 Pins – XC3S1500 / 2000
RS232 I/F XC3S1500 / 2000 PIN
|LV_RX_DATA2 |AB14 |
|LV_TX_DATA2 |AA12 |
|LV_RTS2 |AF16 |
|LV_DCE_READY2 |AD25 |
|LV_CTS2 |AD17 |
Table 10: RS-232 Port 2 Pins – XC3S1500 / 2000
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Figure 5: RS232 Port 1 & 2
RS232 Speed Select Jumper Speed Selected
|J1 – 1 & 2 |1Mbps |
|J1 – 2 & 3 |250Kbps |
|J2 – 1 & 2 |1Mbps |
|J2 – 2 & 3 |250Kbps |
Table 11: RS232 Speed Select Jumper Settings
CAN 2.0B High Speed Transceiver
The Spartan3 – 1500 / 2000 Evaluation Board includes the ST Microelectronics L9616 high speed CAN bus transceiver for implementing and designing with the CAN 2.0B bus controller. Nu Horizons offers a BOSCH compliant CAN 2.0B bus controller that connects to the OPB bus of the Xilinx MicroBlaze soft processor is Figure 4 is a block diagram of the implementation of the CAN 2.0B bus controller and the L9616 high speed transceiver.
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Figure 6: CAN 2.0B Bus Controller & High-Speed Transceiver
The L9616 is a bidirectional transceiver for signal conditioning and processing in connection with a CAN controller. Data rates of up to 1MEGABAUD are supported using either shielded or non-shielded pair of lines. Table 9 details the physical connections to the XC3S1500 / 2000 FPGA.
CAN High Speed Transceiver XC3S1500 / 2000 Pin
|1 – CAN_TX0 |AB23 |
|4 – CAN_RX0 |Y26 |
Table 12: L9616 Connections
J11 ASC Speed Select Jumper Speed Selected
|J11 – 1 & 2 | 40MHz |
|520B-G |LTC1742 | 14 Bit |65Msps |Ain < 40MHz |
|520B-H |LTC1742 | 14 Bit |65Msps |Ain > 40MHz |
|520B-I |LTC1741 |12 Bit |65Msps |Ain < 40MHz |
|520B-J |LTC1741 | 12 Bit |65Msps |Ain > 40MHz |
|520B-K |LTC1743 |12 Bit |50Msps |Ain < 40MHz |
Table 31: LTC High Speed ADC Evaluation Board Part Numbers
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Figure 12: LTC Evaluation Board
Linear Technology High Speed ADC Interface Connections
LTC A/D Interface 1500 / 2000 PIN LTC A/D Interface 1500 / 2000 PIN
|D0 – EXP SLOT_I/O_66 |M1 |D8 – EXP SLOT_I/O_58 |K6 |
|D1 – EXP SLOT_I/O_65 |L7 |D9 – EXP SLOT_I/O_57 |K5 |
|D2 – EXP SLOT_I/O_64 |L6 |D10 – EXP SLOT_I/O_56 |K4 |
|D3 – EXP SLOT_I/O_63 |L5 |D11– EXP SLOT_I/O_55 |K3 |
|D4 – EXP SLOT_I/O_62 |L4 |D12 – EXP SLOT_I/O_54 |K2 |
|D5 – EXP SLOT_I/O_61 |L2 |D13 – EXP SLOT_I/O_53 |K1 |
|D6 – EXP SLOT_I/O_60 |L1 |OF – EXP SLOT_I/O_52 |J7 |
|D7 – EXP SLOT_I/O_59 |K7 |CLK_ADC |AD13 |
Table32: J29 LTC ADC Interface – XC3S1500 / 2000
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Figure 13: J29 Circuit Diagram
Intersil High Speed Digital to Analog Interface
The Spartan 3 - 1500 / 2000 Evaluation Board includes the interface to Intersil high speed DACs ISL5x29EVAL1 evaluation cards for developing high performance DSP applications such as Quadrature Transmit with an IF Range 0 – 80MHz and Medical/Test Instrumentation and Equipment. Table 8 details the available evaluation platforms from Intersil.
Intersil Part Number Number of bits Clock Speed
|ISL5629EVAL1 |2x8 |210MHz |
|ISL5729EVAL1 |2x10 |210MHz |
|ISL5829EVAL1 |2x12 |210MHz |
|ISL5929EVAL1 |2x14 |210MHz |
Table 33: Intersil Evaluation Board Part Numbers
Intersil High Speed DAC Interface Connections
Intersil DAC Signal XC3S1500 / 2000 Pin
|Q_Data_0 - EXP_SLOT_I/O_29 |E1 |
|Q_Data_1 - EXP_SLOT_I/O_28 |D2 |
|Q_Data_2 - EXP_SLOT_I/O_27 |AC2 |
|Q_Data_3 - EXP_SLOT_I/O_26 |AA2 |
|Q_Data_4 - EXP_SLOT_I/O_25 |W3 |
|Q_Data_5 - EXP_SLOT_I/O_24 |U4 |
|Q_Data_6 - EXP_SLOT_I/O_22 |P1 |
|Q_Data_7 - EXP_SLOT_I/O_21 |AC1 |
|Q_Data_8 - EXP_SLOT_I/O_20 |AB4 |
|Q_Data_9 - EXP_SLOT_I/O_19 |AB3 |
|Q_Data_10 - EXP_SLOT_I/O_18 |AB2 |
|Q_Data_11 - EXP_SLOT_I/O_17 |AB1 |
|Q_Data_12 - EXP_SLOT_I/O_16 |AA5 |
|Q_Data_13 - EXP_SLOT_I/O_15 |AA4 |
|CLK - EXP_SLOT_I/O_23 |R2 |
Table 34: J27 Intersil DAC Interface – XC3S1500 / 2000
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Figure14: J27 Circuit Diagram
Intersil DAC Signal XC3S1500 / 2000 Pin
|I_Data_0 - EXP_SLOT_I/O_14 |AA3 |
|I_Data_1 - EXP_SLOT_I/O_13 |AA1 |
|I_Data_2 - EXP_SLOT_I/O_12 |Y7 |
|I_Data_3 - EXP_SLOT_I/O_11 |Y6 |
|I_Data_4 - EXP_SLOT_I/O_10 |Y5 |
|CLK - EXP_SLOT_I/O_8 |Y2 |
|I_Data_6 - EXP_SLOT_I/O_7 |Y1 |
|I_Data_7 - EXP_SLOT_I/O_6 |W7 |
|I_Data_8 - EXP_SLOT_I/O_5 |W6 |
|I_Data_9 - EXP_SLOT_I/O_4 |W5 |
|I_Data_10 - EXP_SLOT_I/O_3 |W4 |
|I_Data_11 - EXP_SLOT_I/O_2 |W2 |
|I_Data_12 - EXP_SLOT_I/O_1 |W1 |
|I_Data_13 - EXP_SLOT_I/O_0 |V7 |
|I_Data_5 - EXP_SLOT_I/O_9 |Y4 |
Table 35: J28 Intersil DAC Interface – XC3S1500 / 2000
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Figure 15: J28 Circuit Diagram
Graphical LCD Interface
The Spartan3 – 1500 / 2000 Evaluation Board interfaces directly to the Logic Product Developments Display Kits, to review the available Display Kits reference
The Spartan3 – 1500 / 2000 Evaluation Board has a 2x30 pin 0.100" header (J31) that connects all of the LCD signals directly from the evaluation boards FPGA. Depending on your specific display, only a few of the LCD signals may be needed. Table details the physical connections to the XC3S1500 / 2000 FPGA. Figure details the connector circuit.
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Figure 16: J31 Circuit Diagram
J31- LCD I/F 1500 / 2000 Pin J31-LCD I/F 1500 / 2000 Pin
|LCD_MOD |D21 |BLUE5 |E16 |
|LCD_SPL |E20 |BLUE4 |F16 |
|LCD_SPS |B21 |BLUE3 |G16 |
|LCD_CLK_RETURN |G19 |BLUE2 |H16 |
|LCD_VEEEN |B22 |BLUE1 |A17 |
|LCD_DON |B20 |BLUE0 |B17 |
|LCD_CLK |B14 |GREEN5 |E17 |
|HSYNC |G18 |GREEN4 |F17 |
|VSYNC |D17 |GREEN3 |G17 |
|LCD_REV |C21 |GREEN2 |B18 |
|LCD_HRLP |B16 |GREEN1 |C18 |
|LCD_PSAVE |A21 |GREEN0 |F18 |
|LCD_CLS |A16 |RED5 |A19 |
|LCD_VDDEN | |RED4 |B19 |
|LCD_MDISP |D20 |RED3 |C19 |
|LCD_PWM |H15 |RED2 |D19 |
|RED0 |F19 |RED1 |E19 |
Table 36: J31 LCD I/F Connections – XC3S1500 / 2000
Agilent Soft Touch Probe Interface
The Spartan3 – 1500 / 2000 Evaluation Board includes the Agilent Soft Touch Probe, E5394A which is a 34-channel single-ended soft touch connectorless probe compatible with all Agilent logic analyzers that have a 40-pin pod connector. It is capable of acquiring data at the maximum rates of the logic analyzer it is connected to.
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Figure 17: Agilent E5394A Soft Touch Probe Connector Diagram
Programming Interface
The Spartan3 1500 / 2000 Evaluation Board supports JTAG configuration by the Xilinx JTAG Cable III (Connector J3) and Cable IV (Connector J4). Table 14 and 15 detail the physical pin connections to the XC3S1500 / 2000 FPGA.
Programming Status LED
LD10 – Programming status LED – Done Pin going high, confirming configuration of the FPGA.
Cable III – J3 XC3S1500 / 2000 PIN
|3 – TCK |B24 |
|4 – TDO |D24 |
|5 – TDI |C1 |
|6 - TMS |A24 |
Table 37: Cable III Interface
Cable IV – J4 XC3S1500 / 2000 PIN
|6 - TCK |B24 |
|8 - TDO |D24 |
|10 – TDI |C1 |
|4 - TMS |A24 |
Table 38: Cable IV Interface
Operating and Storage Environments
Temperature
The HW-AFX-SP3-1500 / 2000 development board can be safely stored at temperatures ranging from -20 – 85º C. The HW-AFX-SP3-1500 / 2000 development board will operate reliably in an ambient temperature of 0 - 70º C.
Humidity
The HW-AFX-SP3-1500 / 2000 development board is reliable in storage and operating in a relative humidity of 10% to 95% non-condensing for the appropriate temperature ranges listed above.
Regulatory Compliance (FCC Part 15 Class B, and Part 68)
This product is sold as an evaluation platform only. No EMI testing was performed.
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