Vel Tech | Private Deemed University , Avadi, Chennai

Design and simulation of pipelined serial adder to add/subtract 8 number of size, 12 bits . each in 2’s compliment . Design and simulation of pipelined parallel adder to add/subtract 8 number of size, 12 bits each in 2’s compliment . Design of traffic light controller using verilog . Testing the traffic controller design using FPGA board ................
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