Lecture 3: Continuation of SystemVerilog

Lecture 3: Continuation of SystemVerilog

Last Lecture

? Talked about combinational logic always statements. e.g.,

module ex2(input logic a, b, c, output logic f);

logic t; // internal signal

always_comb begin

t = a & b; f = t | c; end

endmodule

should use "=" (called "blocking" assignment) in comb. logic always statements. RHS just takes output from the previous equation.

The order of statements matters!

2

This Lecture

? Talk about "clocked always statements", which generate combinational logic gates and flip-flops

? Unfortunately, SystemVerilog does not have welldefined semantics for describing flip-flops and finite state machines (FSMs)

? Instead, SystemVerilog relies on idioms to describe flip-flops and FSMs (i.e., the use of coding templates that synthesis tools will interpret to mean flip-flops and FSMs)

? If you do not follow these "templates", your code may still simulate correctly, but may produce incorrect hardware

3

D Flip-Flop

module flop(input logic

clk,

input logic [3:0] d,

output logic [3:0] q);

always_ff @(posedge clk)

q ................
................

In order to avoid copyright disputes, this page is only a partial summary.

Google Online Preview   Download