EE524/CptS561 Computer Architecture



EE524/CptS561 Computer Architecture Fall 2011

Course Project

You will work in teams of 2 or 3 students. There two options for the project.

Option 1 (Maximum: 2 students) [10% of course grade]

In this option you will write a comprehensive review paper of 10 (or less) pages in the form of an IEEE conference paper. Your team will choose a family of multicore CPUs and provide a description of them. There are four CPU families below, please choose two families (your team’s first and second choices). Within each family there are three processors you are going to describe two of them in your final paper.

A. AMD Processors. Choose two of:

Opteron (3rd generation),

Phenom II, or

Turion X2

B. Intel Processors. Choose two of:

Itanium (9000 series),

Xeon (7400 series), or

Core i7

C. IBM Processors. Choose two of:

Power5,

Power 6, or

Cell BE

D. Sun Processors. Choose two of:

UltraSPARC T1,

UltraSPARC T2, or

SPARC64 VII

Option 2 (Maximum: 3 students) [12% of course grade]

In this option your team will simulate a tournament branch predictor. You will need to write a set of programs to simulate this predictor. The variables include: size of local and global predictors (in terms of number of entries: 128, 512, 1024), number of branches for history in the global predictor (1, 2, 4, and 8). Your team will get a several MIPS benchmark traces that have address, code, and assembly mnemonic of every instruction that is executed (short example is shown on the other side.) Here you will report the mispredictions for different predictor sizes when: only global predictor, only local, combination of both.

Milestones

November 30. Team and project selection is due. Send email by 5pm

December 14. Final report due at 10:10am (time of final exam)

Example of a (very short) trace

2 4013a0 00445004                 SLLV 10, 2, 4        

2 4013a4 01e21823                 SUBU 3, 15, 2        

2 4013a8 02238823                 SUBU 17, 17, 3        

2 4013ac 014b6024                 AND 12, 10, 11        

2 4013b0 03194824                 AND 9, 24, 25        

2 4013b4 012c6825                 OR 13, 9, 12        

2 4013b8 2a210008                 SLTI 1, 17, 8

2 4013bc a20d0000                 SB 13, 16, 0

2 4013c0 26100001                 ADDIU 16, 16, 1

2 4013c4 14200005                 BNE 0, 1, 5

Address code Assembly

Code for simulator (ignore this field)

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