ARM Debugger - Lauterbach

ARM Debugger

Release 02.2022

MANUAL

ARM Debugger

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TRACE32 Documents ......................................................................................................................

ICD In-Circuit Debugger ................................................................................................................

Processor Architecture Manuals .............................................................................................. ARM/CORTEX/XSCALE ...........................................................................................................

ARM Debugger ..................................................................................................................... 1

History ................................................................................................................................ 9

Warning .............................................................................................................................. 9

Introduction ....................................................................................................................... 10

Brief Overview of Documents for New Users

10

Demo and Start-up Scripts

11

Quick Start of the JTAG Debugger .................................................................................. 13

FAQ ..................................................................................................................................... 14

Troubleshooting ................................................................................................................ 15

Communication between Debugger and Processor cannot be established

15

Trace Extensions ............................................................................................................... 16

Symmetric Multiprocessing ............................................................................................. 17

Arm Specific Implementations ......................................................................................... 18

TrustZone Technology

18

Debug Permission

18

Checking Debug Permission

19

Checking Secure State

19

Changing the Secure State from within TRACE32

19

Accessing Memory

19

Accessing Coprocessor CP15 Register

20

Accessing Cache and TLB Contents

20

Breakpoints and Vector Catch Register

20

Breakpoints and Secure Modes

20

big.LITTLE

21

Debugger Setup

21

Consequence for Debugging

22

Requirements for the Target Software

22

?1989-2022 Lauterbach

ARM Debugger | 2

big.LITTLE MP

22

Breakpoints

23

Software Breakpoints

23

On-chip Breakpoints for Instructions

23

On-chip Breakpoints for Data

23

Hardware Breakpoints (Bus Trace only)

25

Example for Standard Breakpoints

26

Complex Breakpoints

32

Direct ICE Breaker Access

32

Example for ETM Stopping Breakpoints

33

Access Classes

34

Coprocessors

42

Accessing Memory at Run-time

44

Semihosting

48

SVC (SWI) Emulation Mode

48

DCC Communication Mode (DCC = Debug Communication Channel)

50

Virtual Terminal

52

Large Physical Address Extension (LPAE)

53

Consequence for Debugging

53

Virtualization Extension, Hypervisor

54

Consequence for Debugging

54

Run-time Measurements

54

Trigger

54

Arm specific SYStem Commands .................................................................................... 55

SYStem.CLOCK

Inform debugger about core clock 55

SYStem.CONFIG.state

Display target configuration 55

SYStem.CONFIG

Configure debugger according to target topology 56

describing the "DebugPort"

65

describing the "JTAG" scan chain and signal behavior

70

describing a system level TAP "MultiTap"

74

configuring a CoreSight Debug Access Port "AP"

76

describing debug and trace "Components"

82

which are "Deprecated"

93

SYStem.CONFIG.EXTWDTDIS

Disable external watchdog 98

SYStem.CONFIG.SMMU

Internal use 99

SYStem.CPU

Select the used CPU 101

SYStem.JtagClock

Define the frequency of the debug port 101

SYStem.LOCK

Tristate the JTAG port 104

SYStem.MemAccess

Run-time memory access 105

SYStem.Mode

Establish the communication with the target 111

SYStem.Option

Special setup 114

SYStem.Option.ABORTFIX

Do not access memory area from 0x0 to 0x1f 114

SYStem.Option.AHBHPROT

Select AHB-AP HPROT bits 114

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ARM Debugger | 3

SYStem.Option.AMBA

Select AMBA bus mode 114

SYStem.Option.ASYNCBREAKFIX

Asynchronous break bugfix 115

SYStem.Option.AXIACEEnable

ACE enable flag of the AXI-AP 115

SYStem.Option.AXICACHEFLAGS

Configure AXI-AP cache bits 115

SYStem.Option.AXIHPROT

Select AXI-AP HPROT bits 116

SYStem.Option.BUGFIX

Breakpoint bug fix 116

SYStem.Option.BUGFIXV4

Asynch. break bug fix for ARM7TDMI-S REV4 116

SYStem.Option.BigEndian

Define byte order (endianness) 118

SYStem.Option.BOOTMODE

Define boot mode 118

SYStem.Option.CINV

Invalidate the cache after memory modification 119

SYStem.Option.CFLUSH

FLUSH the cache before step/go 119

SYStem.Option.CacheParam

Define external cache 119

SYStem.Option.CorePowerDetection

Set methods to detect core power 119

SYStem.Option.DACRBYPASS

Ignore DACR access permission settings 121

SYStem.Option.DAPDBGPWRUPREQ

Force debug power in DAP 121

SYStem.Option.DAP2DBGPWRUPREQ

Force debug power in DAP2 122

SYStem.Option.DAPSYSPWRUPREQ

Force system power in DAP 122

SYStem.Option.DAP2SYSPWRUPREQ

Force system power in DAP2 123

SYStem.Option.DAPNOIRCHECK

No DAP instruction register check 124

SYStem.Option.DAPREMAP

Rearrange DAP memory map 124

SYStem.Option.DBGACK

DBGACK active on debugger memory accesses 124

SYStem.Option.DBGNOPWRDWN

DSCR bit 9 will be set in debug mode 125

SYStem.Option.DBGUNLOCK

Unlock debug register via OSLAR 125

SYStem.Option.DCDIRTY

Bugfix for erroneously cleared dirty bits 125

SYStem.Option.DCFREEZE

Disable data cache linefill in debug mode 126

SYStem.Option.DEBUGPORTOptions

Options for debug port handling 126

SYStem.Option.DIAG

Activate more log messages 127

SYStem.Option.DisMode

Define disassembler mode 128

SYStem.Option.DynVector

Dynamic trap vector interpretation 129

SYStem.Option.EnReset

Allow the debugger to drive nRESET (nSRST) 129

SYStem.Option.ETBFIXMarvell

Read out on-chip trace data 129

SYStem.Option.ETMFIX

Shift data of ETM scan chain by one 130

SYStem.Option.ETMFIXWO

Bugfix for write-only ETM register 130

SYStem.Option.ETMFIX4

Use only every fourth ETM data package 130

SYStem.Option.EXEC

EXEC signal can be used by bustrace 130

SYStem.Option.EXTBYPASS

Switch off the fake TAP mechanism 131

SYStem.Option.FASTBREAKDETECTION

Fast core halt detection 131

SYStem.Option.HRCWOVerRide

Enable override mechanism 131

SYStem.Option.ICEBreakerETMFIXMarvell

Lock on-chip breakpoints 132

SYStem.Option.ICEPICK

Enable/disable assertions and wait-in-reset 132

SYStem.Option.IMASKASM

Disable interrupts while single stepping 132

SYStem.Option.IMASKHLL

Disable interrupts while HLL single stepping 133

SYStem.Option.INTDIS

Disable all interrupts 133

?1989-2022 Lauterbach

ARM Debugger | 4

SYStem.Option.IRQBREAKFIX

Break bugfix by using IRQ 133

SYStem.Option.KEYCODE

Define key code to unsecure processor 134

SYStem.Option.L2Cache

L2 cache used 134

SYStem.Option.L2CacheBase

Define base address of L2 cache register 134

SYStem.Option.LOCKRES

Go to 'Test-Logic Reset' when locked 135

SYStem.Option.MACHINESPACES

Address extension for guest OSes 136

SYStem.Option.MEMORYHPROT

Select memory-AP HPROT bits 137

SYStem.Option.MemStatusCheck

Check status bits during memory access 137

SYStem.Option.MMUPhysLogMemaccess

Memory access preferences 137

SYStem.Option.MMUSPACES

Separate address spaces by space IDs 138

SYStem.Option.MonitorHoldoffTime

Delay between monitor accesses 139

SYStem.Option.MPUBYPASS

Ignore MPU access permission settings 139

SYStem.Option.MultiplesFIX

No multiple loads/stores 139

SYStem.Option.NODATA

No data connected to the trace 139

SYStem.Option.NOIRCHECK

No JTAG instruction register check 140

SYStem.Option.NoPRCRReset

Do not cause reset by PRCR 140

SYStem.Option.NoRunCheck

No check of the running state 140

SYStem.Option.NoSecureFix

Do not switch to secure mode 141

SYStem.Option.OVERLAY

Enable overlay support 142

SYStem.Option.PALLADIUM

Extend debugger timeout 142

SYStem.Option.PC

Define address for dummy fetches 143

SYStem.Option.PROTECTION

Sends an unsecure sequence to the core 143

SYStem.Option.PWRCHECK

Check power and clock 143

SYStem.Option.PWRCHECKFIX

Check power and clock 144

SYStem.Option.PWRDWN

Allow power-down mode 144

SYStem.Option.PWRDWNRecover

Mode to handle special power recovery 145

SYStem.Option.PWRDWNRecoverTimeOut

Timeout for power recovery 145

SYStem.Option.PWROVR

Specifies power override bit 145

SYStem.Option.ResBreak

Halt the core after reset 146

SYStem.Option.ResetDetection

Choose method to detect a target reset 147

SYStem.Option.RESetREGister

Generic software reset 147

SYStem.Option.RESTARTFIX

Wait after core restart 148

SYStem.Option.RisingTDO

Target outputs TDO on rising edge 148

SYStem.Option.ShowError

Show data abort errors 149

SYStem.Option.SOFTLONG

Use 32-bit access to set breakpoint 149

SYStem.Option.SOFTQUAD

Use 64-bit access to set breakpoint 149

SYStem.Option.SOFTWORD

Use 16-bit access to set breakpoint 150

SYStem.Option.SPLIT

Access memory depending on CPSR 150

SYStem.Option.StandByTraceDelaytime

Trace activation after reset 150

SYStem.Option.STEPSOFT

Use software breakpoints for ASM stepping 150

SYStem.Option.SYSPWRUPREQ

Force system power 151

SYStem.Option.TIDBGEN

Activate initialization for TI derivatives 151

SYStem.Option.TIETMFIX

Bug fix for customer specific ASIC 151

?1989-2022 Lauterbach

ARM Debugger | 5

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