Test Board Specifications



PMFE Test Board

Version 1.0

Author Forest Martinez-MCKinney, Lan Zhang, Ned Spencer

The PMFE test board will be used to exercise the PMFE functions and characterize its operations. The board will contain a GLAST detector, and circuitry for calibration. The PMFE Test Board will plug into the headers located on the Xilinx Proto Board breakout area. The PCB will be laid out with the same considerations needed in the MCM: power planes, digital layer, analog layer, power supply filtering, etc.

PMFE

35 PMFE Service Pads & 64 Input Channels

13 Analog Pads:

1. CAL0

2. CAL1

3. CAL2

4. CAL3

5. AVDD

6. GND

7. AVDD2

8. QVDD

9. VREF

10. VTH

11. VS

12. I1

13. I2

22 Digital Pads:

14. PAR_P0

15. PAR_N0

16. PAR_P1

17. PAR_N1

18. PAR_P2

19. PAR_N2

20. PAR_P3

21. PAR_N3

22. PAR_P4

23. PAR_N4

24. PAR_P5

25. PAR_N5

26. PAR_P6

27. PAR_P6

28. PAR_N7

29. PAR_P7

30. CLK_P

31. CLK_N

32. CLK_DATA_P

33. CLK_DATA_N

34. DVDD

35. DGND

Analog Pads

CAL0-CAL3 pads will be connected to an analog mux (ADG734) which will allow pulse generator signals to be sent to one of CAL0-CAL3 inputs while the others are tied to ground to minimize cross talk. The input capacitance of each input should be approximately the number of channels on each bus times the calibration cap on each channel.

Cin=16x50fF=.8nF

AVDD and GND are the analog voltage rails, which need to have 3.3volts across them. The analog voltage will be supplied from the VCCAUX pins on the Proto Board breakout area. The noise on the analog rails must be less than ??mV to minimize error. The larger of the filter caps will be X5R 4.7(F 10V capacitors.

AVDD2 and QVDD require 1.5volts relative to GND. These two inputs can be tied together in the layout. These will be powered from the Xilinx Proto Board by the core logic supply VCCINT. The Proto Board has two stakes headers that will supply this voltage to the PMFE.

VREF and VTH are used to set the comparator voltage. The effective threshold voltage of the comparator stage relative to GND is set with both pads. The potential required for VREF is 1.0 V. The effective voltage

Veffective=VTH-VREF

The method proposed for setting the reference voltage and maintaining good noise isolation is to use an instrumentation amp and for the reference and threshold. The AD620 will be powered from the same bench top supply, +/-5 volts that will power the ADG436. The threshold voltage will be a floating potential supplied to the instrumentation amp.

VS is used to set the polarity of the comparator stage. Depending upon the side of the detector that the PMFE is used to service, P side or N side, the polarity of the shaper pulse will be negative or positive. For the sake of the PMFE test board the trace that this pad is bonded to should connect to the center of three stake headers. Each of the other stakes will be tied to a rail, allowing the pad to be easily pull up or down with a jumper.

The 3.3V and 0.0V level for VS will be supplied from the FPGA. This voltage is available in the break out are of the Proto Board at the VCCAUX headers.

I1 and I2 are input pads for current. These currents will be set with a resister from the VCCAUX on the FPGA board. In layout they require a resister to the AVDD rail. In order to tune the resistance for adjusting the shaper bias, I1, and I2 for something else; we will include a 10 turn pot for the fine adjustments. The 10 turn pot will be a surface mount 3214W 100k pot.

RI1 = 10K+ pot10 turn (20-100K)

RI2 = 10K+ pot10 turn (20-100K)

Digital Pads

PAR _N/P0- PAR _N/P7 are the LVDS data signals. They need to route directly to the PMFE Test Board connector to the Xilinx Proto Board. These are outputs from the PMFE and do not require terminations at the PMFE pads. The Test Board will need to have the terminations placed as close to the connector as possible.

CLK_DATA_N/P make up the frame signal for the PMFE. They need to be routed directly from FPGA. Since they are LVDS inputs to the PMFE, a termination resistance across the PMFE input pads will be required.

CLK_N/P This is the input clock to the PMFE, which is used to clock out the data. They are LVDS inputs to the PMFE and need termination resistance across the PMFE input pads.

DVDD and DGND are the digital voltage rails for the PMFE they will require bypass capacitors for transient currents. The IO Bank supply voltages VCCO_2 and VCCO_3 will be used to power the digital plain on the test board.

Chip Detector Pads:

The detector pads, channel0-cahnnel63, can be wired in 5 ways.

1. Floating

2. One load capacitor CL

3. One calibration capacitor CCAL

4. Both a load and calibration cap

5. Bonding to GLAST Baby Detector

The calibration cap, CCAL needs to large enough for us to saturate the PMFE amplifier. The 300fC must be input through the input channels not the calibration bus. There will need to be an external calibration bus. The bus will consist of a trace route the pulse from a BNC connector though some number of calibration caps to input pads.

ADG436:

An Analog Devices analog switch will be used to route the calibration pulse to the calibration inputs, CAL0-CAL3. The device has two Single Pole Double Throw, SPDT, switches. This device was chosen to the calibration inputs, CAL0-CAL3, to be grounded when they are not receiving the pulse generator signal. The board will require two devices, both operating from dual, +/-5 volt, bench top supplies.

Below is a depiction of the switch structure:

[pic]

The pulse generator output will be connected to the inputs S1A-S2A on each device. These four pins will be tied together then routed to a SMB connector. There will need to be one 50-Ohm termination resister at the SMB input for the pulse to the mux. There is also a need for a channel biasing configuration. That termination will match the 50-Ohm coax from the LeCroy 9210 pulse generator. An additional pull up may be needed with the termination resister. The other inputs, S1B-S2B, will be tied to ground. The switch outputs, D1-D2, will be connected to the CAL0-CAL3 respectively. The mux controls, IN1-IN2, will need to be routed to the FPGA for each device. Since these are slow signals and there will be time to let signals settle in testing, there is no need for terminating resistances at IN1-IN2.

Connectors:

The PMFE test Board will require two SMB connectors and an interface to the Xilinx Proto Board. The SMB connectors are for the calibration pulse inputs. One of will go to the inputs of the switch the other will go to the external calibration bus for larger calibration capacitors. It is likely that a connector will also be needed to deliver +/-5.0 V to the ADG734. The board-to-board connector will be a set of SIP Strip Sockets.

Xilinx Proto Board Header

The Xilinx Proto Board interface will be a bank of headers closest to the edge of the board. The headers connect to specific pins on the FPGA allowing most to be used as IO but also granting access to ground and power. The accessible pins are shown in the spreadsheet below. The pins are located by pin name, i.e. A12, and show available signal, L03N_1.

|FPGA Pins | | | | | | |

| | | | | | |

|  |=Unassinged LVDS Pairs | | | | | | |

Power:

Potentials List:

➢ PMFE

o 3.3V

o 3.3V

o 1.5V

➢ ADG436

o +/-5.0V

The PMFE can, mostly, be powered from the Xilinx Proto Board. There is no +/-5.0V potential on the Proto Board therefore a connector for receiving power from a bench top supply will be necessary. A series ferrite choke for each supply potential is needed for AC isolation. GND and DGND should be at the same DC potential.

Mechanical:

There is an issue of strain relief. The Test Board will plug into 1/10” headers and have a coaxial cable pulling on it; therefore it will need to be secured to the Xilinx Proto Board. The PMFE Test Board will need to have mounting holes for securing the Test Board to the Proto Board. The plated through mounting holes on the Proto Board are connected to the FPGA ground. Perhaps the way to connect the grounds is through the mounting hardware. That would require the Test Board mounting holes to be plated and grounded as well.

The connector will require a considerable amount of force when inserting and removing the Test board from the Proto Broad. A screw jack location on the Test Board will be necessary for the removal of the Test Board form the Proto Board.

The layout of the Test Board will require some special considerations for mounting to detector. The layout must be versatile enough to accommodate both the external calibration capacitors and allow the area to be machined to mount the detector. The detector will need to be biased and the voltages will need to be accessible when the PCB has been machined.

Conclusion:

The PMFE test board will allow the a testing of all the techniques that are required to realize and manage the mixed signal environment of the MCM without the complications of attempting the final system on the first try. If there are unforeseen issues with some aspect of the system they will most likely present themselves in the PMFE Test Board.

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