UNIVERSITY OF CALIFORNIA



UNIVERSITY OF CALIFORNIA

College of Engineering

Department of Electrical Engineering and Computer Sciences

Last modified on October 7, 2002 by Leland Chang (leland@eecs.berkeley.edu)

Borivoje Nikolic Homework #5 EECS 141

Due Tuesday, October 15th, 5pm @ 275 Cory

Problem 1 – Self-loaded Inverter Delay

You would like to find the self-loaded (i.e. no external capacitive load…just the internal capacitances) delay of an inverter fabricated in our not-so-technologically-advanced 2.5V 0.25(m process. However, since you are an EE141 expert, you know that you cannot simply measure this delay in HSPICE with a single unloaded inverter due to problems with Miller multiplication and capacitive coupling. Luckily, you are also an HSPICE expert. So first, you set up a SPICE deck to simulate the following 4-stage inverter chain (with some fanout):

Using this circuit, you can get an accurate measurement of the real delay in a circuit by measuring the delay of the second inverter in the chain. With a reasonable input rise/fall time (~200ps), the first inverter should do a good job of creating a realistic input signal to the second inverter. The third stage provides an appropriate load for the second inverter…because in real life, we would likely be driving some number of gates with an output signal. You put a fourth stage just for good measure…to make sure that the Miller effect for the third stage is reasonable. You also remember to put a reasonable load capacitance (~20fF) at the output of these load inverters so that there is no spurious Miller effect going on. Of course, you don’t forget the fanout of the load inverter stages either. Since there are so many inverters, you know that using the “.SUBCKT” command would make life really easy. You also remember that using the “m” tag (multiplicity parameter) when calling a subcircuit could be helpful.

In order to get the self-loaded delay, you decide to do the following:

a) Use HSPICE to find the average propagation delay (average of low-high and high-low transitions) for an inverter in this process for a fanout of 1, 2, 3, and 4. Simply measured the delay of the second inverter in this chain. Use the SPICE model in ‘/home/ff/ee141/MODELS/g25.mod’. Plot the propagation delay as a function of the fanout.

b) In your plot, the points should fall in a straight line…find the best-fit line through the data. This allows you to extrapolate the delay for a fanout of 0 (intercept with the x-axis). This is your self-loaded delay. What is this value?

c) In your plot, the slope of the line tells you about the additional delay per fanout. What is this value?

d) From your answers to b) and c), find the Cd/Cg, the ratio between the drain capacitance (self-load) and the gate capacitance (load per additional fanout). Assuming that Cg=Cox(Wn+Wp)L, compute Cg and Cd.

e) Using Cd (and Cg if you like), compute Req. Just use the average delay, ignoring differences between high-low and low-high transitions.

Problem 2 – Self-loaded NAND Delay

Since finding the self-loaded inverter delay was so easy for you, you decide to move on to a NAND gate. Again, you use a 4-stage chain…but you have to change the connections a bit to get the three stages flipping around correctly:

a) Use HSPICE to find the average propagation delay for a NAND gate in this process for a fanout of 1, 2, 3, and 4. Plot the propagation delay as a function of the fanout.

b) What is the self-loaded delay of a NAND gate?

c) What is the slope of the best-fit line through your data points (additional delay per fanout)? This slope is related to the number obtained from logical effort calculations when you divide by the slope for an inverter (problem 1)…compare slopeNAND/slopeINV to the theoretical value from logical effort.

d) From your answers to b) and c), find the Cd/Cg. Compute Cg and Cd.

e) Compute Req.

Problem 3 – You Guessed It…Self-loaded NOR Delay

To be complete, you might as well figure out the self-loaded NOR gate delay Again, you use a 4-stage chain…but you have to change the connections a bit to get the three stages flipping around correctly:

a) Use HSPICE to find the average propagation delay for a NOR gate in this process for a fanout of 1, 2, 3, and 4. Plot the propagation delay as a function of the fanout.

b) What is the self-loaded delay of a NOR gate?

c) What is the slope of the best-fit line through your data points (additional delay per fanout)? This slope is related to the number obtained from logical effort calculations when you divide by the slope for an inverter (problem 1)…compare slopeNOR/slopeINV to the theoretical value from logical effort.

d) From your answers to b) and c), find the Cg/Cd. Compute Cg and Cd.

e) Compute Req.

Problem 4 – Investigating Wire Delay in a Pentium 4 Chip…

You are a circuit designer working for a certain microprocessor manufacturer with a green logo. You are trying to figure out some information about the wires on a competitor’s chip that has the words “Pentium 4” scribbled all over it (you know, from the company with the blue logo).

You notice that a two-stage buffer is being used to drive a metal wire stretching all the way across this chip – a distance of ~1.2 cm. By looking under the microscope, you guess that the first inverter is probably of minimum size. You know the chip is fabricated in a 0.13(m process…and that this blue-logo-ed company had presented some information regarding this process at the International Electron Devices Meeting last year (S. Thompson et al., IEDM, 2001, pp. 257-260). From that paper, you can estimate that the input capacitance (Ci) of this minimum-sized inverter would be ~1.5fF while the propagation delay (tp0) would be ~7.0ps when loaded with an identical gate. Your metal wire, which is 0.6(m in width, should have a sheet resistance of ~0.02(/(, a capacitance of ~0.03fF/(m2 and a fringing field capacitance of ~0.02fF/(m. The wire seems to be driving another minimum-sized inverter at the other end.

a) What is the propagation delay through just this metal wire (without considering the buffer)?

b) Under the microscope, it is very difficult to tell the size of the second inverter. However, assuming that the designers at the blue-logo-ed company sized it to minimize total delay (a good assumption, don’t you say?), what is the size of this inverter? What, then, would be the minimum delay through the two-stage buffer?

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Cload

Cload

Cload

4rd stage ensures proper Miller effect on 3rd stage

Cload

Wp/Wn = 2(m/1(m for all inverters

L=0.25(m

Cload

Fanout

Cload

Vdd

Vdd

Vdd

Vdd

Vdd

Cload

Vdd

NAND

in

Vdd

out

Vdd

Cload

Cload

Cload

Cload

Cload

NOR

in

out

Vdd

3rd stage provides appropriate loading

1st stage shapes input signal

Delay

measured here

Cload

VIN

Vdd

Cload

Vdd

Cload

Vdd

Vdd

Vdd

Cload

Wp/Wn = 2(m/2(m for all NAND gates

L=0.25(m

Delay

measured here

Cload

VIN

Wp/Wn = 4(m/1(m for all NOR gates

L=0.25(m

Delay

measured here

Cload

VIN

Fanout

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