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Write VHDL code in Dataflow modeling fora) 3:8 Decoder using Conditional Assignment Statement (i.e. when – else statement)b) 3:8 Decoder using Selected Signal Assignment statement (i.e. with – select statement)a] Q(7) : INPUTS OUTPUTS S(2) : Decoder3to8 S(1) S(0)Q(1)Q(0)Table 1. Truth tableINPUTSOUTPUTSS(2)S(1)S(0)Q(7)Q(6)Q(5)Q(4)Q(3)Q(2)Q(1)Q(0)0000000000100100000010010000001000110000100010000010000101001000001100100000011110000000Above decoder has 3 input lines and 8 output lines. It is also called as binary to octal decoder it takes a 3-bit binary input code and activates one of the 8(octal) outputs corresponding to that code.a] 3:8 Decoder using Conditional Assignment Statement (when-else statement)--VHDL Program for 3:8 Decoder using when-elselibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Decoder3to8 is Port ( S : in STD_LOGIC_VECTOR (2 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0));end Decoder3to8;architecture dataflow of Decoder3to8 isbegin Q <= "00000001" when S="000" else "00000010" when S="001" else "00000100" when S="010" else "00001000" when S="011" else "00010000" when S="100" else "00100000" when S="101" else "01000000" when S="110" else "10000000";end dataflow;b] 3:8 Decoder using Selected Signal Assignment statement (with-select statement)--VHDL Program for 3:8 Decoder using library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Decoder3to8 is Port ( S : in STD_LOGIC_VECTOR (2 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0));end Decoder3to8;architecture dataflow of Decoder3to8is begin with s select Q <= "00000001" when "000", "00000010" when "001", "00000100" when "010", "00001000" when "011", "00010000" when "100", "00100000" when "101", "01000000" when "110", "10000000" when "111", "ZZZZZZZZ" when others;end dataflow; ................
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