The OVSF Code Generator



IEEE P802.15

Wireless Personal Area Networks

|Project |IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) |

|Title |Document for DSSS OVSF Specification |

|Date Submitted |[27 December 2012] |

|Source |Kyung Sup Kwak [ Inha Univ.] |E-mail: [ kskkwak@inha.ac.kr ] |

| |Jaedoo Huh [ ETRI ] |E-Mail: [ jdhuh@etri.re.kr ] |

| |M. Al Ameen [ Inha Univ.] |E-Mail: [ m.ameen@ ] |

|Re: |[TG4k LECIM PHY Draft development] |

|Abstract |LECIM TG4k DSSS OVSF Code Generator |

|Purpose |Draft standard development |

|Notice |This document has been prepared to assist the IEEE P802.15. It is offered as a basis for discussion and is not binding |

| |on the contributing individual(s) or organization(s). The material in this document is subject to change in form and |

| |content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein.|

|Release |The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly |

| |available by P802.15. |

The following is to be incorporated by replacing existing section19.1.2.6.2 of the TG4k draft.

19.1.2.6.2 OVSF Code Generator

Orthogonal variable spreading factor (OVSF) code is the same as Walsh code, except that each sequence has different index number in the code set, which results from their different generator algorithms.

In LECIM system, Gold code is used inside a CLON as the primary code. OVSF code is used to identify the CLONs and clusters to provide double protection from the outside interference.

The OVSF codes can be defined recursively by a tree structure, as shown in Figure 159.

[pic]

Figure 159 –OVSF code tree

The OVSF Code Generator block outputs can be specified by two parameters in the block's mask: the Spreading factor and the Code index. In Figure 66, [pic] is a code of length [pic]at depth [pic] in the tree. The Code index [pic] has the range of [pic], , which specifies how far down the column of the tree at depth [pic] the code appears. The root code [pic] has the length of [pic], the Code index [pic], and the depth [pic]. Two branches, which have the length of [pic], leading out of [pic] are labeled by the sequences [pic] and [pic], where [pic].

To recover the code from the Spreading factor and the Code index, the following procedures are applied. Convert the Code index i into the binary form. If [pic], add zeros to the left side of this binary code index to make it have the[pic] form. To choose the specific code in the tree, the path is determined using the binary path sequence in the form of [pic]. This binary path sequence describes the path from the root to the specific code according to the rule as follows: the path takes the upper branch from the code at depth [pic] if [pic], or the lower branch if [pic] for [pic]. For example, with the root [pic] and [pic] of [pic], then [pic] and [pic] can be defined as: [pic]

To make the above procedures more clear, a specific example is given below. Assuming the finding code has the Spreading factor [pic] and Code index [pic], then the following steps need to be done:

1. Convert [pic] to the binary number 110.

2. Add one 0 to the left to obtain 0110, which has the length of [pic].

3. Construct the sequences [pic] according to the following table.

|Path |Path |Code index |Code [pic] |

|depth |sequence |i | |

|r |xr | | |

|0 | |0 |[pic] |

|1 |0 |0 |[pic] |

|2 |1 |1 |[pic] |

|3 |1 |3 |[pic] |

|4 |0 |6 |[pic] |

4.

Table 159a – Example of OVSF code recovery

From the Table 159a, the code [pic] has Spreading factor [pic] and Code index [pic].

The logical level architecture of OVSF code generator is shown in Figure 159b. There are two inputs for the OVSF code generator: an OVSF Code index [pic] and Spreading factor [pic]. The Code index [pic] is stored in the [pic] binary representation as [pic]. According to the input Spreading factor[pic], the chip rate binary counter counts incrementally from 0 to [pic] in the [pic] binary representation as [pic].

[pic]

Figure 159b – Logical Level architecture of OVSF code generator

[pic]

Figure 159c –An example of OVSF code generator for LECIM DSSS PHY

For example, to generate the code [pic] in Figure 159, considering the digital CMOS logic operation, the mapping {“+1”->”logic 0”}, and {“-1”->”logic 1”} is specified. The participation of the specific bits in the XOR operation according to the OVSF Code index [pic] is periodic in time and can be controlled by the chip rate binary counter as illustrated in Figure 159c and the following table.

Table 159d – Example of OVSF code output

|Chip rate counter |Operation |OVSF code output [pic] |

|[pic] |[pic] | |

| |with code index | |

| |i= 5 | |

| | |CMOS logic mapping form | Form in Figure 159 |

|0 0 0 |0 |0 |1 |

|0 0 1 |[pic] |1 |-1 |

|0 1 0 |[pic] |0 |1 |

|0 1 1 |[pic] |1 |-1 |

|1 0 0 |[pic] |1 |-1 |

|1 0 1 |[pic] |0 |1 |

|1 1 0 |[pic] |1 |-1 |

|1 1 1 |[pic] |0 |1 |

The PIB attributes phyLECIMDSSSPSDUOVSFSpreadingFactor and phyLECIMDSSSPSDUOVSFCodeIndex specify the OVSF code output. The same values shall be used to recover the OVSF code.

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