Wayne M .edu
Wayne M. Morrell
11/14/04
Digital Thermometer Lab Based on an LM34 Temperature Sensor, an ADC0831 Analog-to-Digital Converter, and a Xilinx XC95108 PC84 CPLD
The objective of this lab is to have students complete a CPLD module design that incorporates a comprehensive mixture of combinational and sequential logic circuits and that also controls, senses and uses the output of an external device. The design further introduces an example of a serial IO interface. The object of this design is a simple digital thermometer that can measure temperature in the range of 3°F to 212°F. Sequential logic incorporated are counters, shift registers, and registers. Combinational logic includes a count detector, a binary-to-BCD data conversion module, and two 7-segment decoder modules. A temperature sensor chip converts temperature to a voltage proportional to Fahrenheit temperature. An analog-to-digital converter chip with a serial IO interface controlled by the CPLD module digitizes the temperature sensor output voltage. The CPLD module on a PLDT-3 Trainer then processes the digital data and displays the temperature in decimal on LEDs and a two-digit 7-segment display unit on the PLDT-3 Trainer.
An LM34 temperature sensor chip was chosen because of its simplicity and its linear voltage output relative to temperature. The LM34 temperature sensor chip operates on the same +5V DC power source available on the PLDT-3 Trainer and produces a voltage output equal to 10 mV/°F over a range of -32°F to 212°F (see Figure 1). However, without access to a negative DC voltage, the LM34 operating range is limited to +3°F to 212°F.
An ADC0831 analog-to-digital converter chip was chosen because of its simplicity and its use of a serial IO interface. This chip compares a differential voltage input with a reference voltage and generates an 8-bit binary value expressing the ratio of the voltage input to the reference voltage, where the maximum 8-bit value of 255 represents the reference voltage. As the LM34 temperature sensor output is 10 mV/°F, setting the reference voltage of the ADC chip to 2.55 V causes the output binary value to equal the temperature reading in Fahrenheit. The circuit shown in Figure 2 provides the necessary reference voltage and a means to trim this voltage.
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Sampling of the voltage input and generation of the binary equivalent is triggered by the trailing edge of the first clock pulse (CLK) after the chip select signal (CS) is brought low. The resultant binary value is then transferred serially, MSB first, with the output bits (DO) becoming valid within 1.5 (s of the trailing edges of the next eight clock pulses. Subsequent clock pulses have no further effect until the chip select signal is raised high and then brought low again to start a new cycle (see Figure 3).
The CPLD design is an ABEL program targeted for a Xilinx XC95108 PC84 mounted on a PLDT-3 Trainer. The PLDT-3 Trainer has a 4.0 MHz clock, but the maximum clock speed of the ADC0831 chip is only 400 KHz, so a binary counter is used to divide the clock frequency down to 250 KHz. A 4-bit counter would suffice, but extension of the Clock Divider Counter to eight bits permits generation of chip select and capture signals (see Figure 4).
Because the XC95108 CPLD uses leading edge triggering, the ADC data output (DO) is shifted into shift register S7..S0 of the CPLD using !CLK so that data is sampled on the trailing edge of CLK. This allows maximum settling time for DO. As the last bit is shifted into S7..S0 on the tenth clock following ADC chip select, the value in the shift register is transferred into the Data Capture Register R7..R0 by the eleventh clock, which occurs when C1A.[Q3..Q0] equals 10102.
The output of the Data Capture Register is transferred to the Display Register at the leading edge of the 1 Hz clock provided that the Display Register LOAD signal is true. The LOAD signal is set false whenever the 'Capture' signal is true to avoid transferring data while The Data Capture Register is changing value.
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The output of the Display Register is applied to a Binary-To-BCD Converter Module to generate a BCD value equal to the measured temperature in degrees Fahrenheit. The Binary-To-BCD Converter is a combinational logic analogy of a common iterative algorithm. To convert binary to BCD, the binary value is initially placed to the right of a BCD digit field, then shifted left n times, one bit at a time across the BCD digit field, where n is the bit length of the binary number. Following each shift except the last, the resultant value in each of the BCD digit positions is sampled. If the value sampled is greater than four, that value is increased by three (see Figure 5).
The Binary-To-BCD Converter in this lab uses embedded modules, C1 to C9, to test and conditionally add three to intermediate BCD digit values (see Figure 6). Shifts are performed by shifting the modules to the right rather than shifting the bits left. The first three shifts are performed before the first test by C1 because three bits are needed to exceed a value of four in the units digit position. As the PLDT-3 Trainer can only display two 7-segment digits, the rightmost two bits of the BCD hundreds digit are displayed on LEDs and the BCD tens and units digits are passed to 7-segment decoder modules which then drive the two display digits. This displays the temperature to the nearest degree Fahrenheit.
This lab exemplifies the modular approach to design as it incorporates modules designed in previous labs. Two previously designed 4-bit counters are cascaded to form the Clock Divider Counter. The Data Capture Register and the Display Register are both formed by cascading two 4-bit registers from an earlier lab. The Binary-To-BCD Converter and the 7-segment decoder modules have both been used in earlier labs. This approach facilitates incorporation of a variety of combinational and sequential logic circuits with minimum effort leaving sufficient time to develop a module that controls, senses and uses the output of an external device with a serial IO interface. As a final digital logic lab in the semester, this lab provides an excellent review of earlier labs as well as the introduction of new material.
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References:
1. National Semiconductor. "LM34, Precision Fahrenheit Temperature Sensors." National Semiconductor, 2000. Online. Internet. 14 Nov. 2004. Available:
2. National Semiconductor. "ADC0831/ADC0832/ADC0834/ADC0838, 8-Bit Serial I/O A/D Converters with Multiplexer Options." National Semiconductor, 2002. Online. Internet. 14 Nov. 2004. Available:
3. R.S.R. Electronics. Programmable Logic Device Prototyping Boards. Online. Internet. 14 Nov. 2004. Available:
4. R.S.R. Electronics. "PLDT-3 Trainer User's Manual." R.S.R. Electronics, 2001. Online. Internet. 14 Nov. 2004. Available:
5. Xilinx. "XC95108 In-System Programmable CPLD." Xilinx, Inc., 2003. Online. Internet. 14 Nov. 2004. Available:
6. Haskell, Richard E. and Darrin M. Hanna. "An Introduction to Modern Digital Design." Rochester, MI: Oakland University, 2004.
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CS
CLK
Figure 3. ADC0831 Timing
Figure 6. 9-bit Binary-to-BCD Converter
+5 VDC
6
5
Figure 1. LM34 Temperature Sensor
VOUT = +10 mV/°F)
+VS
(+5V TO +20V)
7
LM34
8
3
4
2
1
CS
GND
VIN (-)
VIN (+)
VREF
DO
TRI-
STATE
DO
7
6
5
4
3
2
1
0
TRI-
STATE
(MSB)
(LSB)
CLK
VCC
Analog-to-Digital
Converter ADC0831
Figure 2. Analog-to-Digital Converter Circuit
22 K(
5.0 K(
Pot.
Xilinx
XC95108
Interface
+5 VDC
BCD Output
Units
Tens
Hundreds
9-bit Binary Input
P10
0
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
B0
B1
B2
B3
B4
B5
B6
B7
B8
0
C6
C9
C5
C8
C4
C7
C3
C2
C1
Binary input: 101100101
shift left 1 01100101
shift left 10 1100101
shift left 101 100101
add 3 +11 :
1000 100101
shift left 1 0001 00101
shift left 10 0010 0101
shift left 100 0100 101
shift left 1000 1001 01
add 3 +11 : :
1011 1100 01
shift left 1 0111 1000 1
add 3 : +11 +11 :
1 1010 1011 1
shift left 011 0101 0111
hundreds tens units
BCD: 3 5 7
Figure 5. Binary-to-BCD Conversion
Voltage
Input
4 MHz
Clock
!Capture
1 Hz
Clock
Capture
(LOAD)
Display Register
R2
LED7,LED8
!CLK
ADC0831
Interface
DO
CS
CLK
Figure 4. Thermometer Logic Block Diagram
a..g
aa..gg
Voltage
Display
CLK
C1A.Q2
C1A.Q3
C1B.Q3
7-Segment
Decoder
7-Segment
Decoder
Count Detect Logic
(C1A.[Q3..Q0] = 10)
(LOAD)
!CLK
!CLK
0
Binary-to-BCD
Converter
Hundreds Tens Units
Data Capture Register R1
Shift Register
S7..S0
Clock Divider
Counter C1A, C1B
Xilinx XC95108
PC84 CPLD
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