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(Department of Computer Science)
WARNING
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Course: Digital Logic Design (3409)
Level: Graduate Semester: Spring, 2020
Total Marks: 100
Pass Marks: 50
ASSIGNMENT No. 1
Note: All questions are compulsory. Each questions carry equal marks.
Q.1 a) Explain the process of following conversions with examples: (20)
i) Hexadecimal to binary
ii) Binary to Octal
b) Covert the following numbers to decimal:
|i. (1110000.110)2 |vi. (566)7 |
|ii. (1222222)3 |vii. (2.776)8 |
|iii. (23231)4 |viii. (88765)9 |
|iv. (43421)5 |ix. (123659)11 |
|v. (0.555)6 |x. (653265)12 |
Q.2 Differentiate the following: (20)
a) Binary Code & Binary Logic
b) BCD counter & Magnitude Compactor
c) ROM & PLA
d) Binary Parallel Adder & Decimal Adder
Q.3 a) Show that the dual of the exclusive-OR equal to its complement. (20)
b) Convert the following to other canonical forms.
i. F (x, y, z) = ∑ (1, 3, 7)
ii. F (A, B, C, D) = ∑ (0, 2, 6, 11, 13, 14)
iii. F (x, y, z) = Π (0, 3, 6, 7)
iv. F (A, B, C, D) = Π (0, 1, 2, 3, 4, 6, 12)
Q.4 Obtain the simplified expression in sum of products for the following Boolean functions: (20)
a) F (x, y, z) = ∑(2, 3, 6, 7)
b) F (A, B, C, D) = ∑(7, 13, 14, 15)
c) F (A, B, C, D) = ∑(4, 6, 7, 15)
d) F (w, x, y, z) = ∑(2, 3,12,13, 14, 15)
Q.5 a) Design a combinational circuit that accepts a three-bit number and generates an output binary number equal to the square of the input number. (20)
b) Implement a Full Subtractor with two half subtractors and an OR gate.
ASSIGNMENT No. 2
Total Marks: 100
Pass Marks: 50
Note: All questions are compulsory. Each questions carry equal marks.
Q.1 a) Design a binary multiplier that multiplies a 4-bit number B = b3b2b1b0 by a 3-bit number a = a2a1a0 to from the product C = c6c5c4c3c2c1c0. This can be done with 12 gates and two 4-bit parallel adders. The AND gates and used to form the products of pairs of bits. (20)
b) Draw the logic diagram of a 2-line to 4-line decoder/de-multiplexer using NOR gates only.
Q.2 a) What is master slave flip-flop? Explain its working with the diagram. (20)
b) Show the logic diagram of a clocked RS-flip-flop with four NAND gates.
Q.3 a) Design the sequential circuit whose state table is given below using a 2-bit register and combinational gages. (20)
|Present State |Input |Next State |
|A |B |x |A |B |
|0 |0 |0 |0 |0 |
|0 |0 |1 |0 |1 |
|0 |1 |0 |1 |0 |
|0 |1 |1 |0 |1 |
|1 |0 |0 |1 |0 |
|1 |0 |1 |1 |1 |
|1 |1 |0 |1 |0 |
|1 |1 |1 |0 |1 |
b) Design a serial adder using a sequential-logic procedure.
Q.4 a) Write down the characteristics and purpose of Multiplexer and bipolar Transistor. (20)
b) Using the actual output transistors of two open-collector TTL gates, show (by means of a truth table) that when connected together to an external resistor and Vcc, the wired connection produces an AND function.
Q.5 Describe the following: (20)
a) Bipolar Transistor
b) Metal Oxide Semiconductor
c) BCD Counter
d) Encoder
3409 Digital Logic Design
|Course Code: |3409 |
|Course Title: |Digital Logic Design |
|Credit Hours: |4 (3 + 1) 3 hours lecture and 3 hours lap per week. |
|Session Offered: |As per offering schedule |
|Recommended Book: |Digital Logic Design by Morris Mano, 4th Edition, 2013. |
|A/V/ Multimedia Content: |N/A |
|Reference Book: |1. Digital Fundamentals, 9E by Thomas L. Floyd Published by Floyd |
| |Publisher, 2007. |
| |2. Fundamental of Digital logic with Verilog Design, Stephen Brown, 2/e, |
| |2007. |
|Computer usage: |3 hours supervised per week + about 3 hours unsupervised lab |
|Evaluation Criteria: |
|i. Assignments and/or quizzes as per instructor’s choice 10% |
|ii. Mid Term Theory/Practical/Presentation/mini projects as per instructor’s choice 20% |
|iii. Final Examination 70% |
Course Outline:
Unit No. 1 Binary System
Binary Numbers Based Conversion of Octal, Hexadecimal and Binary, Complements, Binary Codes, Binary Logic and ICs
Unit No. 2 Boolean Algebra and Logic Gates
Definitions, Theorems and Properties, Boolean Functions, Canonical and STD Forms, other Logical Properties, Gates
Unit No. 3 Simplification of Boolean Function
Map Method, NAND and NOR Implementation, Tabulation Method, Prime Implement
Unit No. 4 Combination Logic
Design Procedure, Adder, Subtractors, Code Conversation Analysis Procedure, NAND and NOR Functions, Ex-OR and Ex-NOR Function
Unit No. 5 Combination Logic with MSI and LSI
Binary Parallel Adder, Decimal Adder, BCD Counter, Magnitude Compactor, Decoders, Demultiplexers, Encoder, Multiplexer, ROM, PLA
Unit No. 6 Sequential Logic
Introduction, Flip Flop, Triggering, State Reduction Excitation Table, Design Procedure, Design of Counter
Unit No. 7 Register, Counter, and Memory Unit
Register Counter, Timing Sequence, Memory Unit
Unit No. 8 Asynchronous Sequential Logic
Analysis Procedure, Circuits with Latches, Design Procedure, Reductions of State and Flow Tables, Race Free State Assignment
Unit No. 9 Digital Integrated Circuits
Bipolar Transistor Characteristics, RTL and DTL Circuits, Transistor, Transistor Logic, Emitter Coupled Logic (ECL), Metal Oxide Semiconductor (MOS), CMOS
Activities / Practical
1. Design an excess -3- to-BCD code converter using a bit full adders MSI circuit.
2. Design a combinational circuit that converts a decimal digit from 8, 4,-2, -1 code to BCD.
3. Draw the logic diagram of a 2-line to 4-line decoder/de-multiplexer using NOR gates.
4. Implement a full-subtractor with two half-subtractor and an OR gate.
5. Design a combinational circuit with four input lines that represent a decimal digit in BCD and four output lines that generates the 9’s complement of the input digit.
6. Draw the logic diagram (showing all gates) of master-slave D flip-flop. Use NAND gates.
Note: The instructors may assign additional activities.
Last revised: June 2015
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