A Typical PC Bus Design - Auckland
A Tour of a Modern PC Motherboard and its Devices
A typical modern computer will contain a motherboard that looks something like the figure below. The motherboard connects all the pieces of the computer together using various busses. The computer has to provide power and typically cooling for the motherboard.
System Architecture
A modern computer system will implement a design similar to that shown below where the devices communicate over busses. We see that the CPU (the main processor) is connected by a front side bus (FSB) to a north bridge chip that connects to memory, graphics (via AGP) and a south bridge. The south bridge is connected to relatively slow devices such as PCI slots, disk drives, keyboards etc.
[pic]
A motherboard for a modern PC
All the data transfers over the main system busses (front side bus, memory bus etc) are synchronised by a system clock. This clock typically runs at ...
66Mhz, 100Mhz or 133 Mhz
Data is sometimes transferred on both the rising and falling edge of the clock signal, giving maximum data transfer rates of up to ... 266 Mhz
Bus Operation – Parallel Data Transfers
The physical bus connections between the processor, north bridge, memory and graphics card etc each consist of an address bus, a data bus, and various control lines.
[pic]
Example: Writing to Memory
When writing to memory, the CPU puts a memory address on to the address bus in order to specify the memory slot (‘1’ in the diagram right). The CPU puts the data onto the data bus (2) and then sets a control line (called the Read/Write Enable line) to indicate to the memory that the data is to written to memory (3). The memory then writes the number into the correct memory slot.
Example: Reading from Memory
When reading a value in from memory, the first step is still to put the correct memory address on the address bus (1 in the diagram). Then the CPU sets the Read/Write Enable control to "Read" (step 2) and the memory puts the correct number on to the data bus (step 3). The processor then reads this value.
Timing on a Bus
If we ask for some data, how do we know when it is ready? There are two solutions to this, being synchronous and asynchronous designs.
Synchronous data transfer:
• Use a system clock
• Components on the bus guarantee to have the data ready on time
Example: Reading memory
[pic]
--------------------------------------------> time
The memory has to guarantee that the data will be ready within 2 clock cycles of a read command being given.
Asynchronous data transfer:
• Use ‘handshaking’, ie wait for a signal that the data is ready.
• A formal ‘protocol’ defines who waits when for what signal
• Communication between a PC and a modem over a serial bus is an example of asynchronous communication
• Timing is now not so crucial
Memory
|[pic] |[pic] |
|Illiac Memory |Core memory (1951) |
| |Memory consisting of tiny magnetic "donuts" at |
| |intersection of a lattice. Could be magnetized |
| |either "clockwise" or "counter-clockwise". Fastest |
| |memory until late 1980's |
|[pic] |
|A modern 256 Mb DDR-SDRAM DIMM (dual inline memory module) |
Different Memory Approaches:
Dynamic random access memory (DRAM)
- has memory cells with a paired transistor and capacitor. The memory requires constant refreshing to keep the capacitor charged. Cheap, and slow.
Static random access memory (SRAM)
- uses multiple transistors, typically four to six, for each memory cell but doesn't have a capacitor in each cell. Fast, but expensive, it is used primarily for cache memory.
Flash RAM
- uses 2 transistors; keeps its values with the power removed. Slow and expensive. Used in USB memory sticks, BIOS, etc
Current RAM technologies:
SD-RAM (Synchronous dynamic random access memory)
- takes advantage of a ‘burst mode’ concept to improve performance by fetching the next bit in sequence before the previous one has finished. The idea is that most of the time the data needed by the CPU will be in sequence. Rate of data transfer set by system clock
DDR-SDRAM (Double Data Rate) SDRAM
- transfers data on both rising and falling edge of system clock, so get a 266 MHz data rate with a 133 MHz system clock
Memory Errors, Parity Bits and Error Correction
The plastic packaging of memory contains small amounts of radioactivity that produce alpha particles. These are energetic, fast moving, helium atoms which are missing their electrons. When an alpha particle emitted by the packaging hits a sense line in the DRAM during a read cycle, the noise it produces causes the sense amplifier to misread the data. With 100 million computers in use today, we should expect roughly 6 million single bit errors per year.
Parity Bits: We can detect memory errors by adding an extra parity bit for every 8 bits of data. Let's look at even parity first. When the 8 bits in a byte receive data, the chip adds up the total number of "1"s. If the total number of "1"s is odd, the parity bit is set to "1." If the total is even, the parity bit is set to "0." When the data is read back out of the bits, the total is added up again and compared to the parity bit. If the total is odd and the parity bit is "1" then the data is assumed to be valid and sent to the CPU. But if the total is odd and the parity bit is "0," the chip knows that there is an error somewhere in the 8 bits and dumps the data. Odd parity works the same way, but the parity bit is set to "1" when the total number of "1"s in the byte are even.
Parity Examples:
|Data |Parity Bit | |Data |Parity Bit |
| |(even parity) | | |(odd parity) |
|10110101 | | |10110101 | |
|10010000 | | |10010000 | |
|11111001 | | |11111001 | |
|10101010 | | |10101010 | |
ECC-RAM uses additional bits to monitor the data in each byte. ECC uses several bits for error checking -- how many depends on the width of the bus -- instead of one. ECC memory uses a special algorithm not only to detect single bit errors, but actually correct them as well. ECC memory will also detect instances when more than one bit of data in a byte fails. Such failures are very rare, and they are not correctable, even with ECC
IO and Other Devices
A typical list of devices is shown below.
[pic]
Each device has a piece of software called a ‘driver’ or ‘device driver’ that is used by the operating system to control the device. The driver simply consists of one or more files containing code.
[pic] [pic]
Each device can claim one or more numbered IO locations from the “Input/Output Range” where data can be read from and written into the device by the CPU. (We already know that IO addresses 37816 and 37916 are part of the parallel port.) Devices can also use interrupts (by claiming a numbered “interrupt request”) and/or DMA (Direct Memory Access) to communicate with the CPU; see next.
[pic] [pic]
CPU Control of Input/Output Devices
There are three common methods for managing input and output operations.
•...PIO = programmed I/O (also known as polling);
•...interrupt driven I/O;
•...direct memory access (DMA).
Programmed I/O (also known as Polling)
•Consider reading a block of data from a device.
•The CPU keeps checking the status of the device until it is ready to be read or written. This is known as a busy-wait.
•When the device is ready the transfer of data is made between the device and CPU.
•After the transfer is completed the CPU checks if there is another communication request for the device. If there is the process repeats, otherwise the CPU continues with another task.
Programmed I/O has several problems:
•...the CPU wastes time polling devices;
•High priority devices are not checked until the CPU is finished with its current I/O task, which may have a low priority.
Interrupt driven I/O
•In interrupt driven I/O the device requests service through a special interrupt request line that goes directly to the CPU.
•The CPU then invokes an interrupt service routine (ISR) for the device and returns to normal execution when the ISR completes.
•With interrupt driven I/O the CPU does not access a device until it needs servicing, so it doesn’t waste time with busy-waits.
Direct memory access (DMA)
•Although interrupt driven I/O frees the CPU until the device requires service, the CPU is still responsible for making the data transfer. All data travels over the bus twice: first to the CPU; then to the destination.
•A DMA device can transfer data directly to and from memory, rather than using the CPU as an intermediary, and can thus relieve congestion on the bus.
[pic]
Input/Output Devices
AGP= Accelerated Graphics Port
The video display card is typically connected by an AGP port to the CPU through the high-speed ‘north bridge’. AGPx4 means 4 times faster than the original AGP standard. The video card can also use the slower PCI bus (see below).
PCI Bus (Peripheral Component Interconnect)
Main way of connecting extra peripherals
Typical devices that use the PCI expansion slots include
Ethernet card
modem
old video cards
EPROM
Flash memory that contains startup code for the BIOS (basic input output system). Bios ‘boots up’ the computer before handing over to the operating system. It also manages the IO. The Bios can be upgraded by ‘flashing’ it with newer software.
Typical IO Ports
[pic][pic]
Communication (Serial) Port (COM1, COM2, …)
- transmits a sequence of single bits, 1 bit at a time
- *asynchronous*/synchronous transfer
- use CTS (clear to send) and RTS (ready to send) lines for ‘handshaking’, ie controlling flow of data.
- uses parity bits to check for errors.
[pic] [pic]
Parallel Port (LPT1, LPT2, etc)
- designed for talking to a printer, typically *asynchronous*/synchronous transfer
- transmits 8 bits to a printer at a time.
- Uses Busy, Strobe and Ack (acknowledge) to handshake.
- Come in traditional, EPP and ECP flavours with varying capabilities.
Pin Description: (don’t learn!)
|Base+0: 8 bit output |Base+2 = Control Port (open collector) |
|Base+1 = Status (input) |Bit7 Reserved |
|Bit7 Busy |Bit6 Reserved |
|Bit6 not ACK |Bit5 Enable Bidirectional |
|Bit5 Paper Out |Bit4 Enable IRQ via ACK |
|Bit4 Select In |Bit3 Select Printer |
|Bit3 not Error |Bit2 Initialize Printer |
|Bit2 not IRQ |Bit1 Auto Linefeed |
|Bit1 Reserved |Bit0 Strobe |
|Bit0 Reserved | |
Disk Drives
Disk drives connect via an IDE or EIDE bus. (ATA33/66/133 = different speed IDE protocols.) New drives use SATA (serial ATA).
[pic]
PIO=…programmed input output
DMA=direct memory access
Magnetic Disk Drives (eg Hard Disk, Hard Drive)
• Long term, nonvolatile storage
• Large, inexpensive, and slow
• Lowest level in the memory hierarchy
Two major types:
• Floppy disk and Hard disk
Both types of disks:
• Rely on a rotating platter coated with a magnetic surface
• Use a moveable read/write head to access the disk
Advantages of hard disks over floppy disks:
• Platters are more rigid ( metal or glass) so they can be larger
• Higher density because it can be controlled more precisely
• Higher data rate because it spins faster
• Can incorporate more than one platter
• Most disks rotate at 3,600 to 7200 RPM
• The smallest item of data that can be read or written is a sector. Many sectors make up a track. Traditionally all tracks have had the same number of sectors, but the sectors per track can change now to make use of the longer tracks near the outside of a disk.
Read/write data is a three-stage process:
• Move the read/write head arm over the proper track
• Wait for the desired sector
to rotate under the read/write head
• Read a sector as it passes under the read-write head
Disk File System:
eg FAT, Fat32, NTFS ………………..…
• Sectors are grouped into clusters, where a cluster is the smallest allocatable unit on the disk.
• File system keeps list of used and unallocated (free) clusters
• A file uses 1 or more clusters.
• File system controls access (open, read, write, close) to files
[pic][pic][pic]
Example: on drive “T:”, any file will take up some multiple of ......8*512bytes=4k.
• Fragmentation
Files end up using sectors (clusters) all over the disk
Run defragmenter to make files contiguous, so run faster
[pic]
Raid
“Redundant array of inexpensive disks”. Connect multiple hard drives together to form what appears to be one drive. Can implement Raid at a range of different levels: (see: )
Striping (Raid 0)
- Spread data across several disk
-Can read/write in parallel, so fast
Mirroring (Raid 1)
-Keep a complete copy of data on two disks
- If one disk dies, data not lost
Redundancy (Raid 3)
Aim to protect against a single drive failing without cost of mirroring
Typically allows ‘…………………………hot-swapping’ - unplug failed drive, plug in new one, while system still up and running.
Redundancy implementation:
Uses XOR to store extra copy of data.
Revision:
|0 |XOR |0 |= | | |
|Data |A |r |s |t |Redundancy Data |
|Hex |65 |114 |115 |116 | 52 |
|Binary |01000001 |01110010 |01110011 |01110100 | 00110100 |
Note: Undo Disk5 calc by XOR with known data; XOR undoes itself!
| |Disk 1 |dead |Disk 3 |Disk 4 |Disk 5 |
|Data |A |? |s |t |Redundancy Data |
|Hex |65 |114 |115 |116 | 52 |
|Binary |01000001 |01110010 |01110011 |01110100 | 00110100 |
Computer Mice
In 1968, at the Fall Joint Computer Conference, Engelbart revealed for the first time such futuristic technology as the mouse, word processing, and on-line networking, technology. This eventually led to the development of the Xerox PARC Star personal computer at Xerox's PARC, which in turn was the inspiration for the Apple Macintosh.
How roller-based Computer Mice Work
by Marshall Brain, From
Mice first broke onto the public stage with the introduction of the Apple Macintosh in 1984, and since then they have helped to completely redefine the way we use computers! Every day of your computing life, you reach out for your mouse whenever you want to move your cursor or activate something. Your mouse senses your motion and your clicks and sends them to the computer so it can respond appropriately.
|Inside a Mouse |[pic] |
|The main goal of any mouse is to translate the motion of your |The guts of a mouse |
|hand into signals that the computer can use. Almost all mice | |
|today do the translation using five components: | |
|A ball inside the mouse touches the desktop and rolls when the|[pic] |
|mouse moves. |The underside of the mouse's logic board. The exposed portion |
| |of the ball touches the desktop |
|Two rollers inside the mouse touch the ball. One of the |[pic] |
|rollers is oriented so that it detects motion in the X |The rollers that touch the ball and detect X and Y motion |
|direction, and the other is oriented 90 degrees to the first | |
|roller so it detects motion in the Y direction. When the ball | |
|rolls, one or both of these rollers roll as well. The | |
|following image shows the two white rollers on this mouse: | |
|The rollers each connect to a shaft, and the shaft spins a |[pic] |
|disk with holes in it. When a roller rolls, its shaft and disk|A typical optical encoding disk. This disk has 36 holes around |
|spin. The following image shows the disk: |its outer edge. |
|On either side of the disk there is an infrared LED and an |[pic] |
|infrared sensor. The holes in the disk break the beam of light|A close-up of one of the optical encoders that track mouse |
|coming from the LED, so that the infrared sensor sees pulses |motion. There is an infrared LED (clear) on one side of the |
|of light. The rate of the pulsing is directly related to the |disk and an infrared sensor (red) on the other. |
|speed of the mouse and the distance it travels. | |
|An on-board processor chip reads the pulses from the infrared |[pic] |
|sensors and turns them into binary data that the computer can |The logic section of a mouse is dominated by an encoder chip, a|
|understand. The chip sends the binary data to the computer |small processor that reads the pulses coming from the infrared|
|through the mouse's cord and PS/2 connector. |sensors and turns them into bytes sent to the computer. You can|
|[pic] |also see the two buttons that detect clicks (on either side of |
|A typical PS/2 Connector. Assume that pin 1 is |the wire connector). |
|located just to the left of the black alignment pin | |
|and the others are numbered clockwise from there. | |
By using two LEDs for each wheel, we can determine the direction the mouse is moving. The simplified figure below shows a wheel in 4 different states, each 15° rotated from the last. Diagram E is equivalent to diagram A, being 60° rotated. For clockwise rotation the states follow each other in order A-B-C-D-E from left to right but if you read the states from right to left, E-D-C-B-A, then these correspond to anticlockwise rotation. These give the timing diagram shown below; read this left to right for the A-B-C-D-E order, and right-to-left for the E-D-C-B-A order.
[pic][pic]
How can we tell which way the mouse is moving?
Whenever a rises, mouse is moving.
If b is high, then moving one way, low moving other way.
LED 2 goes from light to dark, if LED 1 is light then we are rotating clockwise but if
LED 1 is dark, then we have anticlockwise rotation. The computer uses this fact to
monitor direction: each time LED 2 goes from light to dark it samples LED 1 to
determine the direction.
|CPU Evolution | |
|ENIAC (1946) |[pic] |
|Addressable Memory: 200 digits | |
|18,000 vacuum tubes,6,000 switches,10,000 capacitors,70,000 resistors,1,500 | |
|relays | |
|30 tons | |
|10 feet tall x 1,800 square feet | |
|5,000 additions / second | |
|1,000 times faster than any calculating machine before it. | |
| | |
|Intel 4004 (Nov 15 1971) |[pic] |
|•First ever microprocessor | |
|•Clock speed: 108 kHz | |
|•Bus width: 4 bit | |
|•Transistors: 2,300 | |
|•Track width: 10 µm | |
|•Addressable memory: 640 byte | |
|•0.06 MIPS | |
|Intel 8088 (1979) | |
|(used in first IBM PC, 1981) |[pic] |
|Clock speed 4 MHz |First PC – IBM, 1981 |
|0.33 MIPs | |
|Bus width 16 bits (internal) 8 bits (external) | |
|Addressable memory: 1 Mb | |
|Transistors: 29,000 | |
|Track width: 3 µm | |
|The first PC had 16 kByte RAM, expandable to 256k. | |
| | |
|Intel Pentium III (1999) |[pic] |
|•Clock speed: 1 GHz (in 2001) | |
|•Bus width: 64 bit | |
|•Transistors: 9,500,000 | |
|•Track width: 0.25 µm | |
|•Addressable memory: 64 GByte | |
|Intel P4 (2001) |[pic] |
|•Clock speed: 2 GHz ($562, 29 Aug 2001) | |
|•Bus width: 64 bit | |
|•Transistors: 42 million | |
|•Track width: 0.18 µm | |
|•Addressable memory: 64 Gbyte | |
|Volts: 1.75 | |
|Power: 75 Watts | |
|Pentium 4 Prescott 3.4 GHz (2004) |[pic] |
|•Clock speed: 3.4 GHz | |
|•Bus Width: 64 bit | |
|•Transistors: 125 million | |
|•Track Width: 0.09 µm | |
|•Addressable Memory: | |
|•Voltage: 1.385V | |
|•Power: 100 Watts | |
|•Addressable Memory: 64 Gbyte | |
|AMD Processors: | |
| | |
|Athlon XP 2.2 GHz (2003) | |
|•Clock speed: 2.2 | |
|•Bus width: 64 bit | |
|•Transistors: 54 million | |
|•Track width: 0.13 µm | |
|•Addressable memory: 64 Gbyte | |
|•Volts: 1.75 | |
|•Power: 75 Watts | |
| | |
|Athlon XP 64 (2004) | |
|•Clock speed: 2.4 GHz |[pic] |
|•Bus width: 64 bit | |
|•Transistors: 105 million | |
|•Track width: 0.13 µm | |
|•Addressable memory: 1 Terrabyte = 1000 Gbyte | |
|•Volts: 1.75 | |
|•Power: 90 Watts | |
|•Registers: 64 bits | |
|•Direct access to memory (figure below) | |
|[pic] | |
|Moore’s Law |[pic] |
|In 1976, Gordon Moore (CEO, Intel) predicted that the | |
|number of transistors per integrated circuit would double | |
|every 18 months. This prediction appears to still be | |
|correct. | |
|PC |CPUs |Year |Transistor count |
|1st. Generation |8086 and 8088 |1978-81 |29,000 |
|2nd. Generation |80286 |1984 |134,000 |
|3rd. Generation |80386DX and 80386SX |1987-88 |275,000 |
|4th. Generation |80486SX, 80486DX, |1990-92 |1,200,000 |
| |80486DX2 and 80486DX4 | | |
|5th. Generation |Pentium |1993-95 |3,100,000 |
| |Cyrix 6X86 |1996 |-- |
| |AMD K5 |1996 |-- |
| |IDT WinChip C6 |1997 |3,500,000 |
|Improved |Pentium MMX |1997 |4,500,000 |
|5th. Generation |IBM/Cyrix 6x86MX |1997 |6,000,000 |
| |IDT WinChip2 3D |1998 |6,000,000 |
|6th. Generation |Pentium Pro |1995 |5,500,000 |
| |AMD K6 |1997 |8,800,000 |
| |Pentium II |1997 |7,500,000 |
| |AMD K6-2 |1998 |9,300,000 |
|Improved 6th. Generation |Mobile Pentium II |1999 |27,400,000 |
| |Mobile Celeron | |18,900,000 |
| |Pentium III | |9,300,000 |
|7th. Generation |AMD original Athlon |1999 |22,000,000 |
| |AMD Athlon Thunderbird |2000 |37,000,000 |
| |Pentium 4 |2001 |42,000,000 |
|Today |Pentium 4 Prescott |2004 |125,000,000 |
| |Athlon 64 |2004 |105,000,000 |
Major challenge in CPU design:
Possible solutions: lower voltage, smaller chips, cooling!
Over-clocking
-----------------------
[pic][pic]
[pic]
Cylinder: all the tracks under the head at a given point on all surfaces.
[pic][pic]
[pic]
Mice come in all shapes and sizes. This is an older two-button mouse chosen for its simplicity.
[pic]
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