RetroBrew Computers



Working Notes for the N8VEM

Neil Breeden

Table of Contents

N8VEM Port Map 3

Buffered Prototyping Card Jumpers 5

ZILOG Peripherals Board Jumpers and Ports 6

CPU Board Ports 8

FDC (Disk Controller) Board Jumpers 9

VDU Card 12

BUS Monitor Card 14

DSKY 20

DSKY Programming examples in MBASIC 20

Errata 22

Z-80 Based N8VEM CPU Card 22

Z-80 Based N8VEM MINI CPU Card 24

BUS Monitor Card 25

BUS Monitor Card 25

Misc 26

ECB Connector Pinout 26

Bus Monitor Single Step Momentary Switch Connections 27

Serial Cable for the CPU card 28

ROM Images 29

VDU: 29

N8VEM CPU: 29

Notes 32

N8VEM Port Map

|Port (Dec) |Port (Hex) |Card |Function |

|00...31 |$00...$19 | |Open for use – Default for ZILOG Peripheral card |

|32 |$20 |Disk |IDE DATA PORT (LOW BYTE) |

|33 |$21 |Disk |IDE READ: ERROR REGISTER; WRITE: PRECOMP |

|34 |$22 |Disk |IDE SECTOR COUNT |

|35 |$23 |Disk |IDE SECTOR NUMBER |

|36 |$24 |Disk |IDE CYLINDER LOW |

|37 |$25 |Disk |IDE CYLINDER HIGH |

|38 |$26 |Disk |IDE DRIVE/HEAD |

|39 |$27 |Disk |IDE READ: STATUS; WRITE: COMMAND |

|40 |$28 |Disk |IDE DATA PORT (HIGH BYTE) |

|41 |$29 |Disk |IDE (Do not use) |

|42 |$2A |Disk |IDE (Do not use) |

|43 |$2B |Disk |IDE (Do not use) |

|44 |$2C |Disk |IDE (Do not use) |

|45 |$2D |Disk |IDE (Do not use) |

|46 |$2E |Disk |IDE READ: ALTERNATIVE STATUS; WRITE; DEVICE CONTROL |

|47 |$2F |Disk |IDE DRIVE ADDRESS (READ ONLY) |

|48 |$30 |Disk |Floppy (Do not use) |

|49 |$31 |Disk |Floppy (Do not use) |

|50 |$32 |Disk |Floppy (Do not use) |

|51 |$33 |Disk |Floppy (Do not use) |

|52 |$34 |Disk |Floppy (Do not use) |

|53 |$35 |Disk |Floppy (Do not use) |

|54 |$36 |Disk |Floppy MAIN STATUS REGISTER |

|55 |$37 |Disk |Floppy DATA REGISTER |

|56 |$38 |Disk |Floppy (Do not use) |

|57 |$39 |Disk |Floppy (Do not use) |

|58 |$3A |Disk |Floppy CONFIGURATION LATCH |

|59 |$3B |Disk |Floppy (Do not use) |

|60 |$3C |Disk |Floppy PSEUDO DMA ADDRESS |

|61 |$3D |Disk |Floppy (Do not use) |

|62 |$3E |Disk |Floppy (Do not use) |

|63 |$3F |Disk |Floppy (Do not use) |

|64 |$40 |Disk |Floppy (Do not use) |

|65...95 |$41...$59 | |Open for use |

|96 |$60 |CPU |PPI PORTA |

|97 |$61 |CPU |PPI PORTB |

|98 |$62 |CPU |PPI PORTC |

|99 |$63 |CPU |PPI Control |

|100 |$64 |CPU |Do not use |

|101 |$65 |CPU |Do not use |

|102 |$66 |CPU |Do not use |

|103 |$67 |CPU |Do not use |

|104 |$68 |CPU |UART Buffer |

|105 |$69 |CPU |UART Interrupt |

|106 |$6A |CPU |UART Interrupt ID |

|107 |$6B |CPU |UART Line Control |

|108 |$6C |CPU |UART MODEM Control |

|109 |$6D |CPU |UART Line Stat |

|110 |$6E |CPU |UART MODEM Status |

|111 |$6F |CPU |UART Scratch |

|112 |$70 |CPU |RTC Access |

|113 |$71 |CPU |Do not use |

|114 |$72 |CPU |Do not use |

|115 |$73 |CPU |Do not use |

|116 |$74 |CPU |Do not use |

|117 |$75 |CPU |Do not use |

|118 |$76 |CPU |Do not use |

|119 |$77 |CPU |Do not use |

|120 |$78 |CPU |MPCL RAM Latch |

|121 |$79 |CPU |Do not use |

|122 |$7A |CPU |Do not use |

|123 |$7B |CPU |Do not use |

|124 |$7C |CPU |MPCL ROM Latch |

|125 |$7D |CPU |Do not use |

|126 |$7E |CPU |Do not use |

|127 |$7F |CPU |Do not use |

|128...239 |$80...$EF | |Open for use |

|240 |$F0 |VDU |Read VDU |

|241 |$F1 |VDU |Write VDU |

|242 |$F2 |VDU |VDU S Register |

|243 |$F3 |VDU |VDU D Register |

|244 |$F4 |VDU |PPI PORTA |

|245 |$F5 |VDU |PPI PORTB |

|246 |$F6 |VDU |PPI PORTC |

|247 |$F7 |VDU |PPI Control |

|248...255 |$F8...$FF | |Open for use |

Buffered Prototyping Card Jumpers

[pic]

Prototype card pin locations

|SW1 (A7) |SW2 (A6) |SW3 (A5) |SW4 (A4) |Dec |Hex |

|2…3 |2…3 |2…3 |2…3 |0 |$0 |

|2…3 |2…3 |2…3 |1…2 |16 |$10 |

|2…3 |2…3 |1…2 |2…3 |32 |$20 |

|2…3 |2…3 |1…2 |1…2 |48 |$30 |

|2…3 |1…2 |2…3 |2…3 |64 |$40 |

|2…3 |1…2 |2…3 |1…2 |80 |$50 |

|2…3 |1…2 |1…2 |2…3 |96 |$60 |

|2…3 |1…2 |1…2 |1…2 |112 |$70 |

|1…2 |2…3 |2…3 |2…3 |128 |$80 |

|1…2 |2…3 |2…3 |1…2 |144 |$90 |

|1…2 |2…3 |1…2 |2…3 |160 |$A0 |

|1…2 |2…3 |1…2 |1…2 |176 |$B0 |

|1…2 |1…2 |2…3 |2…3 |192 |$C0 |

|1…2 |1…2 |2…3 |1…2 |208 |$D0 |

|1…2 |1…2 |1…2 |2…3 |224 |$E0 |

|1…2 |1…2 |1…2 |1…2 |240 |$F0 |

ZILOG Peripherals Board Jumpers and Ports

[pic]

|SW1 (A7) |SW2 (A6) |SW3 (A5) |SW4 (A4) |BASE PORT (HEX) |BASE PORT (Dec) |

|2-3 |2-3 |2-3 |2-3 |0016 |0 |

|2-3 |2-3 |2-3 |1-2 |1016 |16 |

|2-3 |2-3 |1-2 |2-3 |2016 |32 |

|2-3 |2-3 |1-2 |1-2 |3016 |48 |

|2-3 |1-2 |2-3 |2-3 |4016 |64 |

|2-3 |1-2 |2-3 |1-2 |5016 |80 |

|2-3 |1-2 |1-2 |2-3 |6016 |96 |

|2-3 |1-2 |1-2 |1-2 |7016 |112 |

|1-2 |2-3 |2-3 |2-3 |8016 |128 |

|1-2 |2-3 |2-3 |1-2 |9016 |144 |

|1-2 |2-3 |1-2 |2-3 |A016 |160 |

|1-2 |2-3 |1-2 |1-2 |B016 |176 |

|1-2 |1-2 |2-3 |2-3 |C016 |192 |

|1-2 |1-2 |2-3 |1-2 |D016 |208 |

|1-2 |1-2 |1-2 |2-3 |E016 |224 |

|1-2 |1-2 |1-2 |1-2 |F016 |240 |

Base PORT address settings – 16 total ports are occupied.

|A3 |A2 |Function |HEX |Dec |

|0 |0 |CTC |+0016 |+0 |

|0 |1 |DART |+0416 |+4 |

|1 |0 |PPI #1 |+0816 |+8 |

|1 |1 |PPI#2 |+0C16 |+12 |

Device Offsets

|A1 |A0 |CTC |DART |PPI #1 |PPI #2 |HEX |Dec |

|0 |0 |Channel 0 |UART A Data |Port A Data |Port A Data |+0016 |+0 |

|0 |1 |Channel 1 |UART B Data |Port B Data |Port B Data |+0116 |+1 |

|1 |0 |Channel 2 |UART A Command |Port A Command |Port A Command |+0216 |+2 |

|1 |1 |Channel 3 |UART B Command |Port B Command |Port B Command |+0316 |+3 |

Device Function Offsets

Examples (using pin 1-2 jumpers for SW1..SW4 resulting in base address of 240):

|Desired Function |Base + Device + Function = PORT |

|PPI #1 + PORT A Command |240 + 8 + 2 = 250 |

|CTC + Channel 1 |240 + 0 + 1 = 241 |

[pic]X5 and X6 Jumper setting for DART (SIO/0) Control

X1 – CTC – DART (UART) Port A TTL Levels

X2 – PIO #1

X3 – DART (UART) Port B IEA Levels

X4 – PIO #2

X7 – DART (UART) Port A IEA Levels

CPU Board Ports

The BASE port for the CPU card is hardwired as 6016 or 96 and occupies 32 total PORTS in the range of 6016 thru 7F16 (96 thru 127).

|A4 |A3 |Function |HEX |Dec |

|0 |0 |82C55 PPI |+0016 |+0 |

|0 |1 |UART |+0816 |+8 |

|1 |0 |RTC |+0F16 |+16 |

|1 |1 |CFG |+1816 |+24 |

Device Offsets

|A2 |A1 |

|UART + MODEM Status | 96 + 8 + 6 = 110 |

|RTC + Access RTC | 96 + 16 + 0 = 112 |

|PPI + PORT C | 96 + 0 + 2 = 98 |

|CFG + MPCL RAM Latch | 96 + 24 + 0 = 120 |

|CFG + MPCL ROM Latch | 96 + 24 + 4 = 124 |

Data bit to address mapping for the MPCLs:

|Bit |RAM MPCL |ROM MPCL |

|D0 |A15 |A15 |

|D1 |A16 |A16 |

|D2 |A17 |A17 |

|D3 |A18 |A18 |

|D4 |N/U |A19 |

|D5 |N/U |N/U |

|D6 |N/U |N/U |

|D7 |N/U |ROM Enable |

FDC (Disk Controller) Board Jumpers

[pic]

FDC Board Default Jumper Settings shown in Red

J1 – /INT enable

|Closed |Connect FDC Interrupt to the ECB Interrupt | |

|Open |Disable FDC Interrupt |Default |

J2 – /DSKCHG /RDY I8272

|1-2 |Connect /DSKCHG to /DC/RDY |Default |

|3-4 |Set I8272 RDY Low |Default |

|1-3 |Connect /DSKCHG to Set I8272 RDY | |

|2-4 |Do not connect as this will cause board damage. | |

J3 – Variable Delay Length

|1-2 (0) |1 clock cycle | |

|3-4 (1) |2 clock cycles | |

|5-6 (2) |3 clock cycles | |

|7-8 (3) |4 clock cycles | |

|9-10 (4) |5 clock cycles | |

|11-12 (5) |6 clock cycles |Default |

|13-14 (6) |7 clock cycles | |

|15-16 (7) |8 clock cycles | |

|17-18 (8) |9 clock cycles | |

J4 – Variable Delay Clock Speed

|1-2 |16MHz Clock | |

|2-3 |8MHz Clock |Default |

J5 – /RDY Pull Up Resistor (Floppy PIN 34)

|Closed |Enable the pull up resistor | |

|Open |Disable the pull up resistor |Default |

J6 – Fault Jumper

|1-2 |Enable the /Fault signal | |

|2-3 |Disable the /Fault signal |Default |

J7 – Two Sided

|1-2 |Enable double sided disks | |

|2-3 |Disable double sided disks |Default |

J8 – /WDATE Pull Up resistor

|Closed |Enabled | |

|Open |Disabled |Default |

J9 – /WGATE Pull Up resistor

|Closed |Enabled | |

|Open |Disabled |Default |

J10 – /SIDE Pull Up resistor

|Closed |Enabled | |

|Open |Disabled |Default |

J11 – /HDL Pull Up resistor

|Closed |Enabled | |

|Open |Disabled |Default |

J12 – /VCO Pull Up resistor

|Closed |Enabled | |

|Open |Disabled |Default |

VDU Card

|Jumper |Font Address |Closed |Open |

|P6 |Character EPROM A13 |Default | |

|P7 |Character EPROM A12 |Default | |

|P8 |Character EPROM A11 |Default | |

|Jumper |Function |1-2 |2-3 |

|K1 | | |Closed (Default) |

|K2 | |Closed (Default) | |

|K3* |Light Pen Connector |Open |Open |

[pic]

VDU Card Default Jumpers

The BASE port for the VDU card is hardwired as F016 or 240 and occupies 8 total PORTS in the range of F016 thru F716 (240 thru 247).

|A2 |Function |HEX |Dec |

|0 |VDU |+0016 |+0 |

|1 |8255 PPI |+0416 |+4 |

Device Offsets

|A1 |A0 |VDU |8255 PPI |HEX |Dec |

|0 |0 |Read VDU |Port A |+0016 |+0 |

|0 |1 |Write VDU |Port B |+0116 |+1 |

|1 |0 |VDU S Register |Port C |+0216 |+2 |

|1 |1 |VDU D Register |Control |+0316 |+3 |

Device Function Offsets

VDU Examples (using base port address of 240):

|Desired Function |Base + Device + Function = PORT |

|VDU + Read |240 + 0 + 0 = 240 |

|VDU + Write |240 + 0 + 1 = 241 |

|VDU + S |240 + 0 + 2 = 242 |

|VDU + D |240 + 0 + 3 = 243 |

|PPI + Port A |240 + 4 + 0 = 244 |

|PPI + Port B |240 + 4 + 1 = 245 |

|PPI + Port C |240 + 4 + 2 = 246 |

|PPI + Control |240 + 4 + 3 = 247 |

BUS Monitor Card

|SW_HEX_3_4 |A8...A15 Wait Control |Closed |Open |

|A15 |Feeds SW2 position 1-16 (H4_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A14 |Feeds SW2 position 1-16 (H4_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A13 |Feeds SW2 position 1-16 (H4_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A12 |Feeds SW2 position 1-16 (H4_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A11 |Feeds SW2 position 2-15 (H3_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A10 |Feeds SW2 position 2-15 (H3_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A9 |Feeds SW2 position 2-15 (H3_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A8 |Feeds SW2 position 2-15 (H3_Out) |Compare to Logic 1 |Compare to Logic 0 |

|SW_HEX_1_2 |A0...A7 Wait Control |Closed |Open |

|A7 |Feeds SW2 position 3-14 (H2_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A6 |Feeds SW2 position 3-14 (H2_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A5 |Feeds SW2 position 3-14 (H2_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A4 |Feeds SW2 position 3-14 (H2_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A3 |Feeds SW2 position 4-13 (H1_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A2 |Feeds SW2 position 4-13 (H1_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A1 |Feeds SW2 position 4-13 (H1_Out) |Compare to Logic 1 |Compare to Logic 0 |

|A0 |Feeds SW2 position 4-13 (H1_Out) |Compare to Logic 1 |Compare to Logic 0 |

|SW2 |LED Latch Control |Closed |Open |

|H4_Out |A12...A15 |Enable H4 Comparison |Disable H4 Comparison |

|H3_Out |A8…A11 |Enable H3 Comparison |Disable H3 Comparison |

|H2_Out |A4…A7 |Enable H2 Comparison |Disable H2 Comparison |

|H1_Out |A0…A3 |Enable H1 Comparison |Disable H1 Comparison |

|IN |From SW1 |Enable IN Comparison |Disable IN Comparison |

|N/A | | | |

|N/A | | | |

|N/A | | | |

|SW1 |LED Latch and Wait Control |Closed |Open |

|WAIT |CPU Wait Control |Enable CPU WAIT |Disable CPU Wait |

|N/A | | | |

|WR |CPU Write |Enable WR WAIT |Disable WR Wait |

|MREQ |CPU Memory Request |Enable MQEQ WAIT |Disable MREQ Wait |

|RD |CPU Read |Enable RD WAIT |Disable RD Wait |

|RFSH |CPU Memory Refresh |Enable RFSH WAIT |Disable RFSH Wait |

|IORQ |CPU I/O Request |Enable IORQ WAIT |Disable IORQ Wait |

|M1 |CPU M1 cycle |Enable M1 WAIT |Disable M1 Wait |

[pic]

Bus Monitor Switches

Example Bus Monitor Switch Settings

Single Step on the M1 CPU cycle:

|SW_HEX_3_4 |SW_HEX_1_2 |SW2 |SW1 |

|A15 N/A |A7 N/A |H4_Out Open |WAIT Closed |

|A14 N/A |A6 N/A |H3_Out Open |N/A |

|A13 N/A |A5 N/A |H2_Out Open |WR Open |

|A12 N/A |A4 N/A |H1_Out Open |MREQ Open |

|A11 N/A |A3 N/A |IN Closed |RD Open |

|A10 N/A |A2 N/A |N/A |RFSH Open |

|A9 N/A |A1 N/A |N/A |IORQ Open |

|A8 N/A |A0 N/A |N/A |M1 Closed |

Wait on I/O Requests:

|SW_HEX_3_4 |SW_HEX_1_2 |SW2 |SW1 |

|A15 N/A |A7 N/A |H4_Out Open |WAIT Closed |

|A14 N/A |A6 N/A |H3_Out Open |N/A |

|A13 N/A |A5 N/A |H2_Out Open |WR Open |

|A12 N/A |A4 N/A |H1_Out Open |MREQ Open |

|A11 N/A |A3 N/A |IN Closed |RD Open |

|A10 N/A |A2 N/A |N/A |RFSH Open |

|A9 N/A |A1 N/A |N/A |IORQ Closed |

|A8 N/A |A0 N/A |N/A |M1 Open |

Wait on I/O Requests to port FA16:

|SW_HEX_3_4 |SW_HEX_1_2 |SW2 |SW1 |

|A15 N/A |A7 Closed |H4_Out Open |WAIT Closed |

|A14 N/A |A6 Closed |H3_Out Open |N/A |

|A13 N/A |A5 Closed |H2_Out Closed |WR Open |

|A12 N/A |A4 Closed |H1_Out Closed |MREQ Open |

|A11 N/A |A3 Closed |IN Closed |RD Open |

|A10 N/A |A2 Open |N/A |RFSH Open |

|A9 N/A |A1 Closed |N/A |IORQ Closed |

|A8 N/A |A0 Open |N/A |M1 Open |

Wait on I/O Read Requests to port FA16:

|SW_HEX_3_4 |SW_HEX_1_2 |SW2 |SW1 |

|A15 N/A |A7 Closed |H4_Out Open |WAIT Closed |

|A14 N/A |A6 Closed |H3_Out Open |N/A |

|A13 N/A |A5 Closed |H2_Out Closed |WR Open |

|A12 N/A |A4 Closed |H1_Out Closed |MREQ Open |

|A11 N/A |A3 Closed |IN Closed |RD Closed |

|A10 N/A |A2 Open |N/A |RFSH Open |

|A9 N/A |A1 Closed |N/A |IORQ Closed |

|A8 N/A |A0 Open |N/A |M1 Open |

Wait on I/O Write Requests to port FA16:

|SW_HEX_3_4 |SW_HEX_1_2 |SW2 |SW1 |

|A15 N/A |A7 Closed |H4_Out Open |WAIT Closed |

|A14 N/A |A6 Closed |H3_Out Open |N/A |

|A13 N/A |A5 Closed |H2_Out Closed |WR Closed |

|A12 N/A |A4 Closed |H1_Out Closed |MREQ Open |

|A11 N/A |A3 Closed |IN Closed |RD Open |

|A10 N/A |A2 Open |N/A |RFSH Open |

|A9 N/A |A1 Closed |N/A |IORQ Closed |

|A8 N/A |A0 Open |N/A |M1 Open |

A simple MBASIC program to demonstrate the PORT I/O settings above:

10 PRINT “OUT FA”

15 OUT 250,0

20 PRINT “IN FA”

25 A=INP(250)

30 GOTO 10

Latch LEDs on the M1 CPU cycle:

|SW_HEX_3_4 |SW_HEX_1_2 |SW2 |SW1 |

|A15 N/A |A7 N/A |H4_Out Open |WAIT Open |

|A14 N/A |A6 N/A |H3_Out Open |N/A |

|A13 N/A |A5 N/A |H2_Out Open |WR Open |

|A12 N/A |A4 N/A |H1_Out Open |MREQ Open |

|A11 N/A |A3 N/A |IN Closed |RD Open |

|A10 N/A |A2 N/A |N/A |RFSH Open |

|A9 N/A |A1 N/A |N/A |IORQ Open |

|A8 N/A |A0 N/A |N/A |M1 Closed |

SW_HEX_3_4 A8...A15 Wait Control

Controls the logic levels A8…A15 are compared too, use for setting breakpoints (WAIT) at specific addresses.

|A15 |Used to define the logic level A15 is compared too; use for Address based breakpoints. |

|A14 |Used to define the logic level A14 is compared too; use for Address based breakpoints. |

|A13 |Used to define the logic level A13 is compared too; use for Address based breakpoints. |

|A12 |Used to define the logic level A12 is compared too; use for Address based breakpoints. |

|A11 |Used to define the logic level A11 is compared too; use for Address based breakpoints. |

|A10 |Used to define the logic level A10 is compared too; use for Address based breakpoints. |

|A9 |Used to define the logic level A9 is compared too; use for Address based breakpoints. |

|A8 |Used to define the logic level A8 is compared too; use for Address based breakpoints. |

SW_HEX_1_2 A0...A7 Wait Control

Controls the logic levels A0…A7 are compared too, use for setting breakpoints (WAIT) at specific addresses or for specific PORTs.

|A7 |Used to define the logic level A7 is compared too; use for Address or Port based breakpoints. |

|A6 |Used to define the logic level A6 is compared too; use for Address or Port based breakpoints. |

|A5 |Used to define the logic level A5 is compared too; use for Address or Port based breakpoints. |

|A4 |Used to define the logic level A4 is compared too; use for Address or Port based breakpoints. |

|A3 |Used to define the logic level A3 is compared too; use for Address or Port based breakpoints. |

|A2 |Used to define the logic level A2 is compared too; use for Address or Port based breakpoints. |

|A1 |Used to define the logic level A1 is compared too; use for Address or Port based breakpoints. |

|A0 |Used to define the logic level A0 is compared too; use for Address or Port based breakpoints. |

SW2 LED Latch Control

Controls what signals are routed to the LED Latches on the Bus Monitor card. This is an ‘AND’

function meaning that all enabled signals must be in the MATCH state before the LEDs are latched.

|H4_Out |Controls if the Address comparators for A12…A15 are enabled or not. |

|H3_Out |Controls if the Address comparators for A8…A11 are enabled or not. |

|H2_Out |Controls if the Address/Port comparators for A4…A7 are enabled or not. |

|H1_Out |Controls if the Address/Port comparators for A0…A3 are enabled or not. |

|IN |Controls if the Switch 1 signal comparators are enabled or not (WR/MREQ/RD/RFSH/IORQ/M1) |

|N/A | |

|N/A | |

|N/A | |

SW1 LED Latch and Wait Control

Controls if CPU WAITs are enabled and controls what system signals can cause an LED Latch / WAIT.

|WAIT |Gates the LED Latch to the WAIT logic to enable CPU Wait (breakpoints). |

|N/A | |

|WR |* System write, indicates a memory or port write. |

|MREQ |* Indicates a memory access request is active. |

|RD |* System read, indicates a memory or port read. |

|RFSH |* Memory refresh is active. |

|IORQ |* Indicates an I/O access request is active. |

|M1 |* Indicates the M1 portion of the CPU cycle is active. |

* To enable any of the WR/MREQ/RD/RFSH/IORQ/M1 to generate a LED Latch / WAIT Switch 2 IN must be closed. These signals form an ‘AND’ function meaning if you enable IORQ ‘AND’ WR then the system will WAIT only on PORT Writes. By setting the port address on SW_HEX_1_2 and enabling H1_Out and H2_Out you can breakpoint only on a PORT Write to the port specified on SW_HEX_1_2.

DSKY

The DSKY (DiSplay KeYboard) uses the 8255 PPI on the CPU PCB.

The BASE port for the CPU card is hardwired as 6016 or 96

|A4 |A3 |Function |HEX |Dec |

|0 |0 |82C55 PPI / DSKY |+0016 |+0 |

Device Offsets

|A2 |A1 |A0 |PPI |DSKY |HEX |Dec |

|0 |0 |0 |PORTA |LED Driver Data |+0016 |+0 |

|0 |0 |1 |PORTB |Read KBD Rows |+0116 |+1 |

|0 |1 |0 |PORTC |Bits 0..3: KBD Columns |+0216 |+2 |

| | | | |Bits 4..7: LED Driver Control | | |

|0 |1 |1 |Control |N/U |+0316 |+3 |

DSKY Function Offsets

Examples (using base port address of 96):

|Desired Function |Base + Device + Function = PORT |

|8255 PPI Control | 96 + 0 + 3 = 99 |

|DSKY LED Driver Data | 96 + 0 + 0 = 96 |

|DSKY KBD Rows | 96 + 0 + 1 = 97 |

|DSKY KBD Columns | 96 + 0 + 2 = 98 |

|LED Driver Control | |

DSKY Programming examples in MBASIC

DSKYLED.BAS – Write HEX values to the LEDs (00000000, 11111111 etc.)

10 REM Do something with the DSKY LEDs

20 PPIA=96: REM PPI PORTA

30 PPIB=97: REM PPI PORTB

40 PPIC=98: REM PPI PORTC

50 PPI=99: REM PPI Control

60 OUT PPI,130: REM Set 8255 Control

65 FOR Y=0 TO 15

70 OUT PPIC,192: REM MODE=1 WR=1

80 OUT PPIA,208: REM NORMAL,DECODE,HEX,DATA COMING

90 OUT PPIC,128: REM MODE=1 WR=0

91 OUT PPIC,192: REM MODE=1 WR=1

100 OUT PPIC,64: REM MODE=0 WR=1

110 FOR X=0 TO 7

120 OUT PPIA,128+Y: REM WRITE A NUMBER

130 OUT PPIC,0: REM MODE=0 WR=0

140 OUT PPIC,64: REM MODE=0 WR=1

150 NEXT X

160 OUT PPIC,192: REM MODE=1 WR=1

170 OUT PPIA,80: REM NORMAL,DECODE,HEX,NO DATA COMING

180 OUT PPIC,128: REM MODE=1 WR=0

190 OUT PPIC,192: REM MODE=1 WR=1

192 FOR Z=0 TO 300

193 NEXT Z

200 NEXT Y

210 GOTO 65

DSKYLED.BAS - Alternative line 120 (01234567, 12345678 etc.)

120 OUT PPIA,128+Y+X: REM WRITE A NUMBER

DSKYKBD.BAS – Scan the KBD and print out the col/row when a key is pressed

10 REM Do something with the DSKY KBD

20 PPIA=96: REM PPI PORTA

30 PPIB=97: REM PPI PORTB

40 PPIC=98: REM PPI PORTC

50 PPI=99: REM PPI Control

60 OUT PPI,130: REM Set 8255 Control

70 FOR Y=1 TO 16 STEP 0

80 OUT PPIC,Y: REM Select a Column

81 D=INP(PPIB): REM Read Rows

82 IF D0 THEN PRINT Y,D: REM Did we see a switch closed

83 IF D=0 THEN GOTO 89: REM No switch closed

84 IF D=INP(PPIB) GOTO 83: REM Wait until the switch is released

89 Y=Y*2: REM Move to next column

90 NEXT Y

100 GOTO 70

Errata

Z-80 Based N8VEM CPU Card

• Issue: CPU Clock is not connected to the ECB Backplane connector

• Symptom(s): Add on cards that require the CPU Clock (such as the Zilog Peripherals card and the VDU) do not work.

• Fix: On the Z-80 Based N8VEM CPU card add a jumper wire on the backside of the board from P4 Pin 8 to ECB Connector pin C29.

P4 is the CPU Clock oscillator device, the exact frequency depends on how you built your N8VEM, on the silk screen it is labeled as 4.0000_MHz

• The ECB connector pin out is detailed later in this document.

[pic]

Clock jumper location as seen from the back of the CPU PCB

• Issue: On power up the card doesn’t reset

• Symptom(s): You need to push the reset switch after power up to get the card to initialize.

• Fix: On the Z-80 Based N8VEM CPU card increasing the value of C2 will fix this. I used a 10uF 16V electrolytic capacitor. Smaller values may work as well. I attached the capacitor to the back side of the PCB at the location show below. If you use a polarized capacitor be sure to observe the polarity indicated.

[pic]

[pic]

Z-80 Based N8VEM MINI CPU Card

• Issue: Several ICs are missing their power connections.

o Symptom(s): The card may work but isn’t reliable, or it may refuse to work at all.

o Fix: Install a power jumper on the backside of the card.

[pic]

Jumper location as seen from the back of the MINI PCB

BUS Monitor Card

• Issue: Three ICs are missing their power connections.

o Symptom(s): The card doesn’t work.

o Fix: Install power jumpers on the backside of the card.

U13, U11, and U5 are missing connections to VCC and GND pins and you will have to add jumper wires manually.

If you are assembling your ECB bus monitor, please add the appropriate jumper wires from the bypass capacitor in front of the effected ICs.  With the PCB on its side and DIN 41612 to the right, the top pin of the bypass capacitor is VCC and connects to Pin 14 of the IC.  The bottom pin of the bypass capacitor is GND and connects to pin 7 of the IC.

[pic] Jumper locations as seen from the back of the Bus Monitor PCB

Misc

ECB Connector Pinout

[pic]

Bus Monitor Single Step Momentary Switch Connections

[pic]

Serial Cable for the CPU card

The N8VEM Z-80 CPU card requires a custom made serial cable. In my experience premade cables (10-PIN IDC to DB9) won’t work.

Note: The serial cable for the CPU card will not work with the serial connectors on the ZILOG Peripherals card as the connector pinouts are different.

The connections are as follows:

|Function |N8VEM 10 pin header |9-pin DSUB |

|DSR |2 |4 |

|RX |3 |3 |

|TX |5 |2 |

|DTR |7 |6 |

|GND |9 |5 |

Pictures and more details:







ROM Images

VDU:

80zkuprom.zip contains 80Z.ROM

This is the character generator ROM image.  It was originally designed for a 2716 style EPROM although the VDU uses a 28 pin 27128 EPROM for expansion character sets as it is a more common part.

You load the 2K ROM image at the beginning of the 27128 EPROM.

This EPROM is installed on the VDU PCB.

N8VEM CPU:

Romimage_Feb28_2009.bin as uploaded byDr_Acula

B:\



F:\

autoexec.sub



Instructions for Romimage_Feb28_2009.bin

1) Target is a 27C801 (8MB) EPROM

2) 38400 baud bootup, Drive A-Ram, B=ROM, warm boot skips cpm reload, added tsr routines, show warm boot message, add autoexec and supersub

3) Not enabled – no ide delay (ie set up to use IDE drives if needed), keyboard not enabled, echo off not enabled (only used for radio)

To startup:

1) go to drive B

2) type FORMAT

3) go to drive F

4) PIP A:=B:

5) PIP A:=F:

6) PIP A:=F:

7) PIP A:AUTOEXEC.SUB=F:AUTOEXEC.SUB

Then try a reboot and with battery backed ram supersub should run autoexec.sub and do a directory listing of A:\, then download other files.

Note this is a test romimage and drive F has hardly anything in it.

Romimage_Feb28_2009_TOOLS_Zork.bin as uploaded by nbreeden

B:\



F:\

2400.mac 38400.mac baslib.rel bcload











ws.ovr wsmsgs.ovr

wsprint.ovr



zork1.dat zork2.dat zork3.dat

Instructions for Romimage_Feb28_2009_TOOLS.bin

1) Target is a 27C801 (8MB) EPROM

2) This is the image Romimage_Feb28_2009.bin with additional files added to drive F:

3) 38400 baud bootup, Drive A-Ram, B=ROM, warm boot skips cpm reload, added tsr routines, show warm boot message, add autoexec and supersub

4) Not enabled – no ide delay (ie set up to use IDE drives if needed), keyboard not enabled, echo off not enabled (only used for radio)

ROMIMAGE-DSKY.BIN

A:\



F:\

deblock.asm dump.asm

newrcb.asm print.tst



ws.ins wsmsgs.ovr

wsovly1.ovr

Instructions for ROMIMAGE-DSKY.BIN

1) This is the ROM image for using the DSKY interface

2) Target is a 27C801 (8MB) EPROM

3) 9600 baud bootup

Software:

• Boots to RAM based debug monitor

CP/M 2.2 available at monitor prompt

Virtual Drives:

• A: drive is 32K ROM (10K is system tracks)

• B: drive is 448K RAM (64K of 512K SRAM is dedicated system memory)

• F: drive is 992K ROM (32K is system track)

Notes

FDCMON can be used to format floppy disks: while formatting you will see the following messages:

FORMAT BEGINNING. . .

OPERATION ENDED. . .

01 00 00 02 04 09 02

FORMAT BEGINNING. . .

OPERATION ENDED. . .

05 00 00 02 04 09 02

INVALID COMMAND

80 00 00 02 04 09 02

INTERRUPT NORMAL TERMINATION

21 00 00 02 04 09 02

The “INVALID COMMAND” and “INTERRUPT NORMAL TERMINATION” messages can be ignored as long as you are getting success message from the “FORMAT” block. The “01….” And “05….” messages indicate the tack was successfully formatted (01 for head 00 and 05 for head 01).

-----------------

DW>The difference in the two strings is the bit that is indicating which

head on the floppy it is using.  Seven "status" bytes are returned, but

only the first 3 are actual status, the other bytes are just echoes of

the current state.  The bytes to watch are the status register and the

first three return codes, in this case, there appear to be no errors.

(I would need to revisit the code to be 100% sure, but I think 01 00 and

05 00 are normal termination for heads 00, and 01).

        #1 Status Byte "0"

        #2 Status Byte "1"

        #3 Status Byte "2"

        #4 C - Current Cylinder Number

        #5 H - Current Head

        #6 R - Sector Number

        #7 N - Number of data bytes in sector

DW>> My guess is that it is trying to read the directory from floppy

"A".  If you do not have one on the system, or do not have a 720K floppy

in the drive, it will try for a LONG time.   You should see the codes on

the DSKY TTSSC1C2.

TT=Track

SS=Sector

C1= error code 1

C2= error code 2

If C1 and C2 are anything other than 0, the system it retrying the read.

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