Design Project



Homework 5: Theory of Operation and Hardware Design Narrative Team Code Name: Money Bags Group No. 19Team Member Completing This Homework: Adam HendricksonE-mail Address of Team Member: ahendri@ purdue.eduEvaluation:SECDESCRIPTIONMAXSCORE1.0Introduction 5 2.0Theory of Operation203.0Hardware Design Narrative204.0 Summary55.0List of References10App ASystem Block Diagram10App BSchematic30TOTAL100Comments:IntroductionThe purpose of the Money Bags project is to develop a monopoly game that will be interfaced through a monopoly box via android phones with bluetooth connection. This project will utilize the features in the pic32 microcontroller family to communicate to a bluetooth controller which will determine game advancement. Further, sound will be output via an mpeg decoder for user enjoyment. The board, piece position, and other game information will be output through VGA which will be generated by the microcontroller in conjunction with a Atmel 22V10 pld as well as 1 Megabyte of external video memory. Theory of OperationThe design can be divided easily into several operational sections. These sections include the game logic, bluetooth communication, the mpeg decoder, and the VGA output circuitry. Each subsection plays a unique part in adding to game experience.The game logic will be solely contained on the pic 32 microcontroller. The microcontroller will be clocked at 80MHz in order to facilitate fast drawing to screen and game play. It will be supplied with 3.3V as specified by the manufacturers[1]. The microcontroller will keep track of player position, money, and properties, as well as control who can trade, roll, and will be responsible for determining what will be displayed on the screen. The current state of the game will be determined largely via bluetooth input which will communicate via a bluetooth ic to the microcontroller. This input will allow for players to roll dice as well as make trades. Further, the microcontroller will send game state data back via bluetooth to result in updated game information displayed on android phones. Game logic will determine what images to draw on the screen and will write correct images to the framebuffer on external SRAM in order to update display.The MPEG decoder used will be the STA013 and will be used to output sound via internal speakers. The decoder will communicate to the microcontroller via an I2C connections and will be clocked by a 10Mhz crystal oscillator as specified by the manufacturers. It will be utilize a 3.3V power supply. The mpeg bitstream will be communicated via UART which will also be connected to the microcontroller[2].The bluetooth controller whose output is dictated by the microcontroller will be the TI CC2541. This bluetooth ic will be responsible for sending information from the microcontroller dictated through the game logic, as well as receiving information from the android devices connected to the console. This bluetooth module will be clocked via a 32kz external crystal oscillator as dictated by the manufacturers specifications. It will take 3.3V supply voltage and will transmit and receive signals via a 50 ohm antenna[3]. This component will be communicated through an SPI connection to the microcontroller.The VGA display will be controlled via several components: 2x12-bit asynchronous binary counters, 2x32to16 mux, an 8 bit tristate buffer, 1mb of external SRAM, and a 10 macro cell pld. Each of these ics will be powered by 3.3V in order to keep consistent with other logic and eliminate need for voltage regulators. The 2 counters will be clocked at 25.175MHz pixel clock in order to sequentially access external SRAM. The clock enable and clear pins will be tied to the microcontroller's output compare which will indicate when and image should be drawn on the screen. The counters output will be connected to the 2x32:16 muxs, while the other input will be microcontroller's PortB. These will serve as the address bus for the external SRAM. PortA will also connect to the mux and will serve as the data bus. The select line will be driven through a microcontroller output compare and will only allow microcontroller access to external SRAM when the image is not currently being drawn to screen. The 8 bit tristate will receive input from the mux data line and will have its output enabled when the microcontroller is writing to the external SRAM, which will be determined through the output compare. This will ensure that reads from SRAM will not cause bus fighting. SRAM data output will also be connected to a 10 macro cell Atmel PLD, which will be clock by the 25.175MHz pixel clock and will latch in the pixel data and hold it constant for exactly one cycle to draw the pixel. These components together will ensure a steady constant image. Hardware Design NarrativeThe PIC 32's large number of ports greatly aided in resolving device connectivity issues. The microcontroller's 4 output compares on pins 72, 76-78 were used to generate the HSYNC, HSYNC_EN, V_SYNC, and DRAW_EN signals[1]. These signals are needed in order to correctly display the VGA image. Output compares were chosen because they could compare either timer 2 or timer 3 and would allow the microcontroller to generate VGA control signals without taking up any computing time. Timer 2 and timer 3 will also be utilized on the microcontroller. The timer 2 clock input, T2CK on pin 6, allows for an external clock source to increment the timer. This will conveniently allow the pixel clock to directly control the output compares and allow timer 2 to count to 800 with the 25.175MHz pixel clock indicating 1 scan line of VGA[1]. Timer 3 will be clocked with the HSYNC output compare on its T3CK input on pin 7. This will allow timer 3 to count to 525 to keep track of what row is currently being drawn and when to produce VSYNC signal.Pins 24 and 25, PGEC and PGED will be connected to the programmer and allow for serial programming and debugging. These are located on RB0 and RB1. RB(2:15) will be used as outputs for sending 14 the lower 14 bits of address data to external SRAM. The remaining 6 bits will come from RD(15:10) which will serve as the upper 6 bits. The address needs to be split up as there is no 20 bit port on the PIC32[1]. Pins 52(SDA3) and 53(SCL3) will be used to communicate with the bluetooth controller via I2C. Pins 66 and 67 will communicate with send commands to the MPEG decoder via I2C, while pins 10(SCK2) and 12(SDO2) will send the data stream serially to the decoder[1,2].The PIC 32 reference manual suggests that 0.1uF ceramic capacitors be connected to all VDD ports. There should be a 4.7 to 47 uF bulk capacitor placed as close to the microcontroller as possible to improve power supply stability[1]. SummaryThe monopoly circuit is easily divided into different functional components that each contribute to gaming experience. These include game logic on the microcontroller, VGA output generation, audio decoding and output, and bluetooth transmission/reception. Each of these functional components utilize different features of the PIC 32 microcontroller and demonstrate the true versatility and functionality of the PIC 32 microcontroller family. 5.0 List of ReferencesMicrochip Technology Inc. (2011). PIC32MX5XX/6XX/7XX Family Data Sheet [pdf online]. Available: . (2004, February). MPEG 2.5 LAYER III AUDIO DECODER [pdf online]. Available: Instruments. (2012, November). 2.4-GHz Bluetooth low energy and Proprietary System-on-Chip [pdf online]. Available: Instruments. (2005, May). 12-BIT Asynchronous Binary Counters [pdf online]. Available: Instruments. (2005, April). Octal Transparent D-type Latches with 3-state Outputs [pdf online]. Available: . (2008, June). 1M x8 HIGH-SPEED CMOS STATIC RAM [pdf online]. Available: . (2008, October). QUICKSWITCH PRODUCTS 2.5V/3.3V 32:16 MUX/DEMUX HIGH BANDWIDTH BUS SWITCH [pdf online]. Available: A: System Block DiagramAppendix B: SchematicAUDIOBLUETOOTHPIC32ProgrammerVGABluetooth/MPEG/PIC32AUDIOBLUETOOTHVGA ................
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