A Survey of DDFS Architecture and Implementation



ECE 734 Project Proposal (10/2000)

Huaibin Yang, ID 9017919045

Emal: hyang@cae.wisc.edu

A Survey of DDFS Architecture and Implementation

Background

Fast frequency switching is crucially important in modern wireless communication systems such as TDMA/CDMA digital cellular systems and spectrum-spread wireless LANs. For example, the TDMA system may require that the carrier frequency have to be switched during a signal slot, that is, the change must be accomplished within 100us. Linear phase shifting is also crucial in any system that uses phase shift keying modulation techniques. Such system includes IS-95, IS-94, GSM, DCS-1800, CDPD and several others.

Direct Digital Frequency Synthesizer (DDFS) can achieve fast frequency switching in small frequency steps, over a wide band. Also it provides linear phase and frequency shifting with good spectral purity. So, DDFS is best suited to use in the above communication systems. A further requirement for DDFS is low power consumption budget, especially for portable wireless terminals.

Motivation

I have discussed fundamental frequency synthesizer techniques, Phase Lock Loop (PLL) and DDFS in the ‘in-class presentation’, and focused on the basic DDFS architectures such as RAM-based and phase accumulated methods as well as some implementation examples of DDFS building blocks. A fully pipelined FA architecture for phase accumulator is presented. A simplified ROM look-up table model, aimed at reducing table size to meet power consumption budget in wireless transceivers, is introduced to give an overall conclusion that ROM size is one of the key considerations in DDFS implementation. Along this direction, I hope do more exploration on this special topic.

Project Objective

This course project intends to be survey type. I will focus to discuss the low power DDFS architecture and implementation.

In the first part of the project, basic DDFS concept, design and performance analysis will be presented based on some frequency synthesizer books ([1], [2]). Then I will review some “classic” papers ([3], [4]) in terms of a historical view to understand DDFS technology development and new ideas (almost all papers about DDFS cite [3] at the first place). Then with above background knowledge, the main part of the project comes to explore the most newly papers ([5], [6], [7], [8], [9], some will be added into this list during the progress of the project), which bring new architectures and implementations to reduce power consumption of DDFS in wireless applications. The book ([10]) addresses almost every topic about DDFS and collects the bunch of papers before 1996. It is a good reference if extending the discussion of DDFS further not only for low power implementation. Conclusion and some discussions will be given in the last part of project report.

PROJECT REPORT

ABSTRACT

Direct Digital Frequency Synthesizer (DDFS) can achieve fast frequency switching in small frequency steps, over a wide band. Also it provides linear phase and frequency shifting with good spectral purity. J.Tierney proposed the DDFS idea in 1971[3]. With development of VLSI technology and requirement of modern communication systems, since 1980’s, DDFSs have been widely used in wireless transceivers and many kinds of frequency synthesizer systems especially which impose high demands on frequency synthesizer’ agility.

A standard DDFS architecture consists of accumulator, ROM lookup table, DAC and some reconstruction filters. [1] gives the analysis of spurious effects due to phase truncation of accumulator and finite word length effects of ROM lookup table. Among all building blocks of DDFS, ROM represents both power and performance bottlenecks [11]. Reducing ROM size and power dissipation level are main concerns in this survey.

Early techniques to reduce ROM size are Sunderland’s architecture [12], which leads to 50% reduction of ROM size. Nicolas’s architecture [13] is a further optimization and enhancement of Sunderland’s. In the recent decade, many efforts have been done to change their architectures to get smaller ROM, and even ROM-less. Bellaouar ([5], [7]) proposed a new architecture of only 16-point small lookup-table size, used in wireless communication. Yamagishi [8] observed that reducing the bit number of ROM output is more effective than reducing ROM storage size in decreasing the power dissipation level, so his implementation aims at smaller number of ROM output bit. Hegazi [9] found that traditional DDFS architecture has different number of sine wave samples when DDFS outputs different frequencies. He introduced a method of generating the fixed number of sine wave samples for different output frequencies. Based on this point, his implementation is ROM-less. So far, all DDFS’s architectures are ROM-based. Mortezapour [6] gave the most dramatic change to the traditional DDFS architecture. That is, replacing the ROM with a Non-linear DAC. The phase accumulator’s outputs will be directly as the inputs of a non-linear DAC for generating sine wave. So, the design of non-linear DAC becomes the key consideration in his paper.

The remaining part of this survey is organized as the following three sections. Section I introduces basic DDFS concepts; Section II surveys ROM compression techniques; Section III illustrates two ROM-less designs.

SECTION I: DDFS Introduction

Basic concept

A basic diagram for the standard DDFS is shown in Figure 1. Almost all DDFS are composed of these same fundamental building blocks, although with some enhancements or modifications. J.Tierney presented the idea at [3] in 1971.

[pic]

It uses an M-bit accumulator and a sine function ROM lookup table. This block is clocked with frequency Fclk. For each of clock period, the M-bit input word is added to the accumulator. The output of the accumulator addresses the ROM lookup table to generate a K-bit digitized sine value. Then this value is converted to an actual analog voltage by D/A converter. Since the DDFS is essentially a sampled system, the D/A output should normally be passed through a reconstruction filter, which removes unwanted alias frequencies. Finally, the D/A output is passed through an ideal hard limiter in order to remove any residual AM that may be present.

The minimum frequency resolution of the DDFS is

[pic].

The output frequency is given as

[pic]

where FIW is frequency input word.

Design considerations

Representation of the Ideal DDFS Output Spectrum

[pic],

where h(t) represents the output sample-and-hold, h(t) = 1 for [pic]and 0 otherwise.

Tc = fclk –1 .

1. Phase Truncation Related Spurious Effects

If M of FIW is large, it is impractical that the bit width of the accumulator feedback input is M. Usually, we use W ................
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